Q2a: FSM

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module top_module (
    input clk,
    input resetn,    // active-low synchronous reset
    input [3:1] r,   // request
    output [3:1] g   // grant
);

    parameter A = 2'd0, B = 2'd1;
    parameter C = 2'd2, D = 2'd3;
    reg [1:0] current_state, next_state;

    always @(*) begin
        case(current_state)
            A:begin
                if(r[1] == 1'b1) begin
                    next_state = B;
                end
                else if(r[2] == 1'b1) begin
                    next_state = C;
                end
                else if(r[3] == 1'b1) begin
                    next_state = D;
                end
                else begin
                    next_state = A;
                end
            end
            B:       next_state = r[1] ? B : A;
            C:       next_state = r[2] ? C : A;
            D:       next_state = r[3] ? D : A;
            default: next_state = A;
        endcase
    end

    always @(posedge clk) begin
        if(~resetn) begin
            current_state <= A;
        end
        else begin
            current_state <= next_state;
        end
    end

    assign g[1] = current_state == B;
    assign g[2] = current_state == C;
    assign g[3] = current_state == D;

endmodule