Q3b:FSM

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module top_module (
    input clk,
    input reset,   // Synchronous reset
    input x,
    output z
);

    parameter S0 = 3'b000, S1 = 3'b001, S2 = 3'b010;
    parameter S3 = 3'b011, S4 = 3'b100;
    reg [2:0] current_state, next_state;

    always @(*) begin
        case(current_state)
            S0:     next_state = x ? S1 : S0;
            S1:     next_state = x ? S4 : S1;
            S2:     next_state = x ? S1 : S2;
            S3:     next_state = x ? S2 : S1;
            S4:     next_state = x ? S4 : S3;
            default:next_state = S0;
        endcase
    end

    always @(posedge clk) begin
        if(reset)begin
            current_state <= S0;
        end
        else begin
            current_state <= next_state;
        end
    end

    always @(posedge clk) begin
        if(reset)begin
            z <= 1'b0;
        end
        else begin
            case(next_state)
                S3:     z <= 1'b1;
                S4:     z <= 1'b1;
                default:z <= 1'b0;
            endcase
        end      
    end

endmodule