Consider a finite state machine with inputs s and w. Assume that the FSM begins in a reset state called A, as depicted below. The FSM remains in state A as long as s = 0, and it moves to state B when s = 1. Once in state B the FSM examines the value of the input w in the next three clock cycles. If w = 1 in exactly two of these clock cycles, then the FSM has to set an output z to 1 in the following clock cycle. Otherwise z has to be 0. The FSM continues checking w for the next three clock cycles, and so on. The timing diagram below illustrates the required values of z for different values of w.
Use as few states as possible. Note that the s input is used only in state A, so you need to consider just the w input.
考慮一個具有輸入 s 和 w 的有限狀態機。假設 FSM 以名為 A 的復位狀態開始, 如下圖所示。只要 s = 0,FSM 就會保持在狀態 A,當 s = 1 時,它會移動到狀態 B。一旦進入狀態 B,FSM 就會在接下來的三個狀態中檢查輸入 w 的值 時鐘週期。如果 w = 1 恰好是其中兩個時鐘週期,則 FSM 必須在下一個時鐘週期中將輸出 z 設定為 1。否則,z 必須為 0。FSM 繼續檢查 w 接下來的三個時鐘週期,依此類推。下面的時序圖說明了所需的值 的 z 表示不同的 w 值。
使用盡可能少的狀態。請注意,s 輸入僅在狀態 A 中使用,因此您只需要考慮 w 輸入。
題目網站
module top_module (
input clk,
input reset, // Synchronous reset
input s,
input w,
output z
);
parameter A=2'b00,B=2'b01,C=2'b10,D=2'b11;
reg [1:0] state,next,count;
always@(*)
begin
case(state)
A:next = s ? B : A;
B:next = C;
C:next = D;
D:next = B;
endcase
end
always@(posedge clk)
begin
if(reset)
state = A;
else
begin
if(state == A)
count = 2'b0;
else if(state == B)
count = w;
else
count = count + w;
state = next;
end
end
always@(*)
begin
z = (state == B && count == 2);
end
endmodule
自己寫的在波形圖不匹配,問題在於,希望在B狀態進行復雜描述,反而出錯。這裡參考了CSDN上的一個寫法。
CSDN網站
if(state == A)
count = 2'b0;
else if(state == B)
count = w;
else
count = count + w;
state = next;
這裡的處理方法挺好的,是自己沒有想到的,我是想用卡諾圖實現,但沒能成功。