This is a Moore state machine with two states, two inputs, and one output. Implement this state machine.
This exercise is the same as fsm2, but using synchronous reset.
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module top_module(
input clk,
input reset, // Synchronous reset to OFF
input j,
input k,
output out); //
parameter OFF=0, ON=1;
reg state, next_state;
always @(*) begin
// State transition logic
case(state)
OFF:begin
next_state=(j)?ON:OFF;
end
ON:begin
next_state=(k)?OFF:ON;
end
endcase
end
always @(posedge clk) begin
// State flip-flops with synchronous reset
if(reset)begin
state<=OFF;
end
else begin
state<=next_state;
end
end
// Output logic
// assign out = (state == ...);
assign out=(state==OFF)?0:1;
endmodule
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