Simple FSM 3（asynchronous reset）

江左子固發表於2024-04-14
See also: State transition logic for this FSM

The following is the state transition table for a Moore state machine with one input, one output, and four states. Implement this state machine. Include an asynchronous reset that resets the FSM to state A.

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module top_module(
    input clk,
    input in,
    input areset,
    output out); //

    parameter A=2'b00,B=2'b01,C=2'b10,D=2'b11;
    reg [1:0]state,next_state;
    // State transition logic
    always@(*)begin
        case(state)
            A:begin
                next_state=(in)?B:A;
            end
            B:begin
                next_state=(in)?B:C;
            end
            C:begin
                next_state=(in)?D:A;
            end
            D:begin
                next_state=(in)?B:C;
            end
        endcase
    end
    // State flip-flops with asynchronous reset
    always@(posedge clk or posedge areset)begin
        if(areset)begin
            state<=A;
        end
        else begin
            state<=next_state;
        end
    end
    // Output logic
    assign out=(state==D)?1:0;
    
endmodule

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