FSM:The complete FSM

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module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output shift_ena,
    output counting,
    input done_counting,
    output done,
    input ack );
    reg [3:0] state,next_state;
    parameter [3:0] S = 4'd0,S1 = 4'd1,S11 = 4'd2,S110 = 4'd3,B0 = 4'd4,B1 = 4'd5,B2 = 4'd6,B3 = 4'd7,Count = 4'd8,Wait = 4'd9;
    // state transfer
    always@(*) begin
        case(state)
            S: begin
                next_state = (data)? S1:S;
            end
            S1: begin
                next_state = (data)? S11:S;
            end
            S11: begin
                next_state = (data)? S11:S110;
            end
            S110: begin
                next_state = (data)? B0:S;
            end
            B0: begin
                next_state = B1;
            end
            B1: begin
                next_state = B2;
            end
            B2: begin
                next_state = B3;
            end
            B3: begin
                next_state = Count;
            end
            Count: begin
                next_state =(done_counting)? Wait:Count; 
            end
            Wait: begin
                next_state =(ack)? S:Wait; 
            end
        endcase
    end
    // flip-flop
    always@(posedge clk) begin
        if(reset)
            state <= S;
        else 
            state <= next_state;
    end
    // output
    assign shift_ena = (state == B0 || state == B1 || state == B2 || state == B3)? 1'b1:1'b0;
    assign counting = (state == Count)? 1'b1:1'b0;
    assign done = (state == Wait)? 1'b1:1'b0;
    
endmodule