Q8:Design a Mealy FSM

Implement a Mealy-type finite state machine that recognizes the sequence "101" on an input signal named x. Your FSM should have an output signal, z, that is asserted to logic-1 when the "101" sequence is detected. Your FSM should also have an active-low asynchronous reset. You may only have 3 states in your state machine. Your FSM should recognize overlapping sequences.

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狀態機如下：

module top_module (
    input clk,
    input aresetn,    // Asynchronous active-low reset
    input x,
    output z ); 
	
    parameter idle=4'b0001,
    		one=4'b0010,
    		two=4'b0100,
    		three=4'b1000;
    reg [3:0]state,nstate;
    
    always@(*)begin
        case(state)
            idle:nstate=(x==1)?one:idle;
            one:nstate=(x==1)?one:two;
            two:nstate=(x==1)?three:idle;
            three:nstate=(x==1)?one:two;
            default:nstate=idle;
        endcase
    end
    
    always@(posedge clk or negedge aresetn)begin
        if(!aresetn)begin
            state<=idle;
        end
        else begin
            state<=nstate;
        end
    end
    assign z=(state==two&&x==1);
endmodule