Simple FSM 3（synchronous reset）

江左子固發表於2024-04-14

module top_module(
input clk,
input in,
input reset,
output out); //

parameter A=2'b00,B=2'b01,C=2'b10,D=2'b11;
reg [1:0]state,next_state;
// State transition logic
always@(*)begin
    case(state)
        A:begin
            next_state=(in)?B:A;
        end
        B:begin
            next_state=(in)?B:C;
        end
        C:begin
            next_state=(in)?D:A;
        end
        D:begin
            next_state=(in)?B:C;
        end
    endcase
end
// State flip-flops with synchronous reset
always@(posedge clk)begin
    if(reset)begin
        state<=A;
    end
    else begin
        state<=next_state;
    end
end
// Output logic
assign out=(state==D)?1:0;

endmodule

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