This is a Moore state machine with two states, two inputs, and one output. Implement this state machine.
This exercise is the same as fsm2s, but using asynchronous reset.
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module top_module(
input clk,
input areset, // Asynchronous reset to OFF
input j,
input k,
output out); //
parameter OFF=0, ON=1;
reg state, next_state;
always @(*) begin
// State transition logic
case(state)
OFF:begin
if(j)begin
next_state=ON;
end
else begin
next_state=OFF;
end
end
ON:begin
if(k)begin
next_state=OFF;
end
else begin
next_state=ON;
end
end
endcase
end
always @(posedge clk, posedge areset) begin
// State flip-flops with asynchronous reset
if(areset)begin
state<=OFF;
end
else begin
state<=next_state;
end
end
// Output logic
// assign out = (state == ...);
assign out=(state==OFF)?0:1;
endmodule