From a 1000 Hz clock, derive a 1 Hz signal, called OneHertz, that could be used to drive an Enable signal for a set of hour/minute/second counters to create a digital wall clock. Since we want the clock to count once per second, the OneHertz signal must be asserted for exactly one cycle each second. Build the frequency divider using modulo-10 (BCD) counters and as few other gates as possible. Also output the enable signals from each of the BCD counters you use (c_enable[0] for the fastest counter, c_enable[2] for the slowest).
The following BCD counter is provided for you. Enable must be high for the counter to run. Reset is synchronous and set high to force the counter to zero. All counters in your circuit must directly use the same 1000 Hz signal.
module bcdcount (
input clk,
input reset,
input enable,
output reg [3:0] Q
);
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1 module top_module (
2 input clk,
3 input reset,
4 output OneHertz,
5 output [2:0] c_enable
6 ); //
7 wire[3:0] one, ten, hundred;
8 assign c_enable = {one == 4'd9 && ten == 4'd9, one == 4'd9, 1'b1};
9
10 assign OneHertz = (one == 4'd9 && ten == 4'd9 && hundred == 4'd9);
11
12 bcdcount counter0 (clk, reset, c_enable[0], one);
13 bcdcount counter1 (clk, reset, c_enable[1], ten);
14 bcdcount counter2 (clk, reset, c_enable[2], hundred);
15
16 //bcdcount counter0 (clk, reset, c_enable[0]/*, ... */);
17 //bcdcount counter1 (clk, reset, c_enable[1]/*, ... */);
18
19 endmodule
再寫：
assign c_enable = {one == 4'd9 && ten == 4'd9, one == 4'd9, 1'b1};的理解。
答：首先要理解c_enable的作用，可以理解為這個計數器的小時、分鐘、秒，這三個部分，每一個部分想啟動一次計數，都要有這部分對應的enable來作為使能訊號。聯絡現實生活的時間計數（只不過這裡是10倍10倍的計數，而不是60），秒的部分自然是每個週期都要運作，分鐘的部分要在第10個週期，也即one == 4'd9，小時的部分要在第100個週期，也即one == 4'd9 && ten == 4'd9，因為呼叫的是bcd計數器，記不到100，只能10x10的來計數。
assign OneHertz = (one == 4'd9 && ten == 4'd9 && hundred == 4'd9);的理解。
答：實現了“從 1000 Hz 時鐘中，匯出一個 1 Hz 訊號，稱為 OneHertz”的功能。