Counter 1-12

江左子固發表於2024-04-10
Design a 1-12 counter with the following inputs and outputs:

Reset Synchronous active-high reset that forces the counter to 1
Enable Set high for the counter to run
Clk Positive edge-triggered clock input
Q[3:0] The output of the counter
c_enable, c_load, c_d[3:0] Control signals going to the provided 4-bit counter, so correct operation can be verified.
You have the following components available:

the 4-bit binary counter (count4) below, which has Enable and synchronous parallel-load inputs (load has higher priority than enable). The count4 module is provided to you. Instantiate it in your circuit.
logic gates
module count4(
	input clk,
	input enable,
	input load,
	input [3:0] d,
	output reg [3:0] Q
);
The c_enable, c_load, and c_d outputs are the signals that go to the internal counter's enable, load, and d inputs, respectively. Their purpose is to allow these signals to be checked for correctness.

題目網站

 1 module top_module (
 2     input clk,
 3     input reset,
 4     input enable,
 5     output [3:0] Q,
 6     output c_enable,
 7     output c_load,
 8     output [3:0] c_d
 9 ); //
10   　assign c_enable = enable;
11     assign c_load = reset | ((Q == 4'd12) && (enable == 1'b1));
12     assign c_d = c_load ? 4'd1 : 4'd0;
13     
14     count4 the_counter (clk, c_enable, c_load, c_d , Q);
15 
16     //count4 the_counter (clk, c_enable, c_load, c_d /*, ... */ );
17 
18 endmodule

再寫：

題目翻譯過來就是用一個提供的4位的二進位制加法計數器，完成一個1-12的12位加法計數器

總模組與引用的二進位制計數器，在埠上的關係如下：

  1. 使能端共用，故assign c_enable = enable;

  2. （透過設定高位保持計數器執行的）c_load段，受三個的控制，第一種情況還是reset，一旦高位reset出現，c_load置零，意味停止此次計數；第二種情況是已經計數到了12，也即Q==4'd12，且使能端繼續高位，將要繼續計數，那麼這時意味將要結束這一輪的計數，準備開始下一輪計數，故c_load置零

  3. c_d

很有意思的一點在於，c_d在我打錯的情況下，寫作assign c_d = c_load ? 4'd1 : 4'd1;，也是能夠執行且不報錯的

疑問：

  1. 為什麼定義輸出的c_d，用輸入的d來例項化

  2. c_d有什麼作用

  3. 對於網上的一些寫法有爭議

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