Build a counter that counts from 0 to 999, inclusive, with a period of 1000 cycles. The reset input is synchronous, and should reset the counter to 0.
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module top_module (
input clk,
input reset,
output [9:0] q);
always @(posedge clk) begin
if(reset) begin
q <= 10'd0;
end
else if(q == 10'd999) begin
q <= 10'd0;
end
else begin
q <= q + 1'b1;
end
end
endmodule