Slow decade counter

Build a decade counter that counts from 0 through 9, inclusive, with a period of 10. The reset input is synchronous, and should reset the counter to 0. We want to be able to pause the counter rather than always incrementing every clock cycle, so the slowena input indicates when the counter should increment.

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 1 module top_module (
 2     input clk,
 3     input slowena,
 4     input reset,
 5     output [3:0] q);
 6 always @(posedge clk)begin
 7         if(reset)begin
 8             q<=4'b0;
 9         end
10         else if(slowena)begin
11             if(q==4'd9)begin
12                 q<=4'b0;
13             end
14             else begin
15                 q<=q+1'b1;
16             end
17         end   //等於是一個大巢狀，在大巢狀下再檢查一下reset不等於1
18     end
19 
20 endmodule

用slowena控制在當前狀態是否要進行遞增操作，由圖可以看出，當slowena==0，q保持狀態不變，當slowena==1，q在下一個週期遞增，加1，因為實在下一個週期改變，所以採用時序邏輯