多通道的AXI仲裁方法V3

NoNounknow發表於2024-04-13

https://www.cnblogs.com/VerweileDoch/p/18030653

V2。

讀

module  Aribe_state_rd #(
        parameter integer M_AXI_ID_WIDTH                    = 1          ,
        parameter integer M_AXI_ADDR_WIDTH                  = 32         ,
        parameter integer M_AXI_DATA_WIDTH                  = 64         ,
        parameter integer M_AXI_AWUSER_WIDTH                = 0          ,
        parameter integer M_AXI_ARUSER_WIDTH                = 0          ,
        parameter integer M_AXI_WUSER_WIDTH                 = 0          ,
        parameter integer M_AXI_RUSER_WIDTH                 = 0          ,
        parameter integer M_AXI_BUSER_WIDTH                 = 0          
    )(
        input    wire                              I_clk                       ,
        input    wire                              I_Rst_n                     ,
        //Port                 
        //ch0                  
        input    wire                              I_ch0_req                   ,
        input    wire                              I_ch0_start                 ,
        input    wire                              I_ch0_end                   ,
        output   wire                              O_ch0_vaild                 ,
        //ch1                  
        input    wire                              I_ch1_req                   ,
        input    wire                              I_ch1_start                 ,
        input    wire                              I_ch1_end                   ,
        output   wire                              O_ch1_vaild                 ,
        //ch2                  
        input    wire                              I_ch2_req                   ,
        input    wire                              I_ch2_start                 ,
        input    wire                              I_ch2_end                   ,
        output   wire                              O_ch2_vaild                 ,
        //ch3                  
        input    wire                              I_ch3_req                   ,
        input    wire                              I_ch3_start                 ,
        input    wire                              I_ch3_end                   ,
        output   wire                              O_ch3_vaild                 ,
    //CH0
        input    wire [M_AXI_ID_WIDTH-1 : 0]       CH0_M_AXI_ARID              ,
        input    wire [M_AXI_ADDR_WIDTH-1 : 0]     CH0_M_AXI_ARADDR            ,
        input    wire [7 : 0]                      CH0_M_AXI_ARLEN             ,
        input    wire [2 : 0]                      CH0_M_AXI_ARSIZE            ,
        input    wire [1 : 0]                      CH0_M_AXI_ARBURST           ,
        input    wire                              CH0_M_AXI_ARLOCK            ,
        input    wire [3 : 0]                      CH0_M_AXI_ARCACHE           ,
        input    wire [2 : 0]                      CH0_M_AXI_ARPROT            ,
        input    wire [3 : 0]                      CH0_M_AXI_ARQOS             ,
        input    wire [M_AXI_ARUSER_WIDTH-1 : 0]   CH0_M_AXI_ARUSER            ,
        input    wire                              CH0_M_AXI_ARVALID           ,
        output   reg                               CH0_M_AXI_ARREADY           ,
            
        output   reg  [M_AXI_ID_WIDTH-1 : 0]       CH0_M_AXI_RID               ,
        output   reg  [M_AXI_DATA_WIDTH-1 : 0]     CH0_M_AXI_RDATA             ,
        output   reg  [1 : 0]                      CH0_M_AXI_RRESP             ,
        output   reg                               CH0_M_AXI_RLAST             ,
        output   reg  [M_AXI_RUSER_WIDTH-1 : 0]    CH0_M_AXI_RUSER             ,
        output   reg                               CH0_M_AXI_RVALID            ,
        input    wire                              CH0_M_AXI_RREADY            ,
    //CH1
        input    wire [M_AXI_ID_WIDTH-1 : 0]       CH1_M_AXI_ARID              ,
        input    wire [M_AXI_ADDR_WIDTH-1 : 0]     CH1_M_AXI_ARADDR            ,
        input    wire [7 : 0]                      CH1_M_AXI_ARLEN             ,
        input    wire [2 : 0]                      CH1_M_AXI_ARSIZE            ,
        input    wire [1 : 0]                      CH1_M_AXI_ARBURST           ,
        input    wire                              CH1_M_AXI_ARLOCK            ,
        input    wire [3 : 0]                      CH1_M_AXI_ARCACHE           ,
        input    wire [2 : 0]                      CH1_M_AXI_ARPROT            ,
        input    wire [3 : 0]                      CH1_M_AXI_ARQOS             ,
        input    wire [M_AXI_ARUSER_WIDTH-1 : 0]   CH1_M_AXI_ARUSER            ,
        input    wire                              CH1_M_AXI_ARVALID           ,
        output   reg                               CH1_M_AXI_ARREADY           ,
            
        output   reg  [M_AXI_ID_WIDTH-1 : 0]       CH1_M_AXI_RID               ,
        output   reg  [M_AXI_DATA_WIDTH-1 : 0]     CH1_M_AXI_RDATA             ,
        output   reg  [1 : 0]                      CH1_M_AXI_RRESP             ,
        output   reg                               CH1_M_AXI_RLAST             ,
        output   reg  [M_AXI_RUSER_WIDTH-1 : 0]    CH1_M_AXI_RUSER             ,
        output   reg                               CH1_M_AXI_RVALID            ,
        input    wire                              CH1_M_AXI_RREADY            ,
    //CH2
        input    wire [M_AXI_ID_WIDTH-1 : 0]       CH2_M_AXI_ARID              ,
        input    wire [M_AXI_ADDR_WIDTH-1 : 0]     CH2_M_AXI_ARADDR            ,
        input    wire [7 : 0]                      CH2_M_AXI_ARLEN             ,
        input    wire [2 : 0]                      CH2_M_AXI_ARSIZE            ,
        input    wire [1 : 0]                      CH2_M_AXI_ARBURST           ,
        input    wire                              CH2_M_AXI_ARLOCK            ,
        input    wire [3 : 0]                      CH2_M_AXI_ARCACHE           ,
        input    wire [2 : 0]                      CH2_M_AXI_ARPROT            ,
        input    wire [3 : 0]                      CH2_M_AXI_ARQOS             ,
        input    wire [M_AXI_ARUSER_WIDTH-1 : 0]   CH2_M_AXI_ARUSER            ,
        input    wire                              CH2_M_AXI_ARVALID           ,
        output   reg                               CH2_M_AXI_ARREADY           ,
            
        output   reg  [M_AXI_ID_WIDTH-1 : 0]       CH2_M_AXI_RID               ,
        output   reg  [M_AXI_DATA_WIDTH-1 : 0]     CH2_M_AXI_RDATA             ,
        output   reg  [1 : 0]                      CH2_M_AXI_RRESP             ,
        output   reg                               CH2_M_AXI_RLAST             ,
        output   reg  [M_AXI_RUSER_WIDTH-1 : 0]    CH2_M_AXI_RUSER             ,
        output   reg                               CH2_M_AXI_RVALID            ,
        input    wire                              CH2_M_AXI_RREADY            ,
    //CH3
        input    wire [M_AXI_ID_WIDTH-1 : 0]       CH3_M_AXI_ARID              ,
        input    wire [M_AXI_ADDR_WIDTH-1 : 0]     CH3_M_AXI_ARADDR            ,
        input    wire [7 : 0]                      CH3_M_AXI_ARLEN             ,
        input    wire [2 : 0]                      CH3_M_AXI_ARSIZE            ,
        input    wire [1 : 0]                      CH3_M_AXI_ARBURST           ,
        input    wire                              CH3_M_AXI_ARLOCK            ,
        input    wire [3 : 0]                      CH3_M_AXI_ARCACHE           ,
        input    wire [2 : 0]                      CH3_M_AXI_ARPROT            ,
        input    wire [3 : 0]                      CH3_M_AXI_ARQOS             ,
        input    wire [M_AXI_ARUSER_WIDTH-1 : 0]   CH3_M_AXI_ARUSER            ,
        input    wire                              CH3_M_AXI_ARVALID           ,
        output   reg                               CH3_M_AXI_ARREADY           ,
            
        output   reg  [M_AXI_ID_WIDTH-1 : 0]       CH3_M_AXI_RID               ,
        output   reg  [M_AXI_DATA_WIDTH-1 : 0]     CH3_M_AXI_RDATA             ,
        output   reg  [1 : 0]                      CH3_M_AXI_RRESP             ,
        output   reg                               CH3_M_AXI_RLAST             ,
        output   reg  [M_AXI_RUSER_WIDTH-1 : 0]    CH3_M_AXI_RUSER             ,
        output   reg                               CH3_M_AXI_RVALID            ,
        input    wire                              CH3_M_AXI_RREADY            ,
    //result
        output   reg  [M_AXI_ID_WIDTH-1 : 0]       M_AXI_ARID                  ,
        output   reg  [M_AXI_ADDR_WIDTH-1 : 0]     M_AXI_ARADDR                ,
        output   reg  [7 : 0]                      M_AXI_ARLEN                 ,
        output   reg  [2 : 0]                      M_AXI_ARSIZE                ,
        output   reg  [1 : 0]                      M_AXI_ARBURST               ,
        output   reg                               M_AXI_ARLOCK                ,
        output   reg  [3 : 0]                      M_AXI_ARCACHE               ,
        output   reg  [2 : 0]                      M_AXI_ARPROT                ,
        output   reg  [3 : 0]                      M_AXI_ARQOS                 ,
        output   reg  [M_AXI_ARUSER_WIDTH-1 : 0]   M_AXI_ARUSER                ,
        output   reg                               M_AXI_ARVALID               ,
        input    wire                              M_AXI_ARREADY               ,
            
        input    wire [M_AXI_ID_WIDTH-1 : 0]       M_AXI_RID                   ,
        input    wire [M_AXI_DATA_WIDTH-1 : 0]     M_AXI_RDATA                 ,
        input    wire [1 : 0]                      M_AXI_RRESP                 ,
        input    wire                              M_AXI_RLAST                 ,
        input    wire [M_AXI_RUSER_WIDTH-1 : 0]    M_AXI_RUSER                 ,
        input    wire                              M_AXI_RVALID                ,
        output   reg                               M_AXI_RREADY                
);

    //-----------------------------------------------------------------//
        localparam  state_idle  = 10'b0000_0000_01;
        localparam  state_aribe = 10'b0000_0000_10;

        localparam  state_ch0_0 = 10'b0000_0001_00;
        localparam  state_ch0_1 = 10'b0000_0010_00;

        localparam  state_ch1_0 = 10'b0000_0100_00;
        localparam  state_ch1_1 = 10'b0000_1000_00;

        localparam  state_ch2_0 = 10'b0001_0000_00;
        localparam  state_ch2_1 = 10'b0010_0000_00;

        localparam  state_ch3_0 = 10'b0100_0000_00;
        localparam  state_ch3_1 = 10'b1000_0000_00;

    //-----------------------------------------------------------------//
        //req
            //step.0
            wire    [3:0]   single_req_Concat           ;
            reg     [7:0]   double_req_Concat           ;
            //step.1
            reg     [7:0]   S1_req_Concat               ;
            //step.2
            reg     [7:0]   S2_req_Concat               ;
            //step.3
            wire    [3:0]   S3_req_Concat               ;
        //aribe
            wire            aribe_start                 ;
            wire            aribe_step                  ;
            reg             aribe_cycle                 ;
            reg     [3:0]   aribe_value                 ;
        //step
            reg     [3:0]   step                        ;
        //state
            reg     [9:0]   state                       ;
            wire            aribe_ch0_end               ;
            wire            aribe_ch1_end               ;
            wire            aribe_ch2_end               ;
            wire            aribe_ch3_end               ;
        //req vaild
            reg             reg_ch0_vaild               ;
            reg             reg_ch1_vaild               ;
            reg             reg_ch2_vaild               ;
            reg             reg_ch3_vaild               ;
        //start
            reg             r1_ch0_start                ;
            reg             r2_ch0_start                ;

            reg             r1_ch1_start                ;
            reg             r2_ch1_start                ;

            reg             r1_ch2_start                ;
            reg             r2_ch2_start                ;

            reg             r1_ch3_start                ;
            reg             r2_ch3_start                ;
    //-----------------------------------------------------------------//
    assign  single_req_Concat = {I_ch3_req, I_ch2_req, I_ch1_req, I_ch0_req};
    assign  aribe_start  = |single_req_Concat;
    assign  aribe_step   = (aribe_start == 1'b1 && aribe_cycle == 1'b0);

    assign  aribe_ch0_end = (I_ch0_end == 1'b1)&&(state == state_ch0_1);
    assign  aribe_ch1_end = (I_ch1_end == 1'b1)&&(state == state_ch1_1);
    assign  aribe_ch2_end = (I_ch2_end == 1'b1)&&(state == state_ch2_1);
    assign  aribe_ch3_end = (I_ch3_end == 1'b1)&&(state == state_ch3_1);

    assign O_ch0_vaild  = reg_ch0_vaild;
    assign O_ch1_vaild  = reg_ch1_vaild;
    assign O_ch2_vaild  = reg_ch2_vaild;
    assign O_ch3_vaild  = reg_ch3_vaild;

    always @(posedge I_clk) begin
        step[3:0] <= {step[2:0],aribe_step};
    end

    // Pose
    always @(posedge I_clk) begin
        {r2_ch0_start,r1_ch0_start} <= {r1_ch0_start,I_ch0_start};
        {r2_ch1_start,r1_ch1_start} <= {r1_ch1_start,I_ch1_start};
        {r2_ch2_start,r1_ch2_start} <= {r1_ch2_start,I_ch2_start};
        {r2_ch3_start,r1_ch3_start} <= {r1_ch3_start,I_ch3_start};
    end

    // aribe_cycle
    always @(posedge I_clk) begin
        if(I_Rst_n == 1'b0) begin
            aribe_cycle <= 1'b0;
        end else if(aribe_ch0_end|aribe_ch1_end|aribe_ch2_end|aribe_ch3_end) begin
            aribe_cycle <= 1'b0;
        end else if(aribe_start == 1'b1 && aribe_cycle == 1'b0 && state == state_idle) begin
            aribe_cycle <= 1'b1;
        end else begin
            aribe_cycle <= aribe_cycle;
        end
    end

    // step.0
    always @(posedge I_clk) begin
        if(I_Rst_n == 1'b0) begin
            double_req_Concat <= 'd0;
        end else if(aribe_step == 1'b1 && step[0] == 1'b0) begin
            double_req_Concat <= {2{I_ch3_req, I_ch2_req, I_ch1_req, I_ch0_req}};
        end else begin
            double_req_Concat <= double_req_Concat;
        end
    end

    // step.1
    always @(posedge I_clk) begin
        if(I_Rst_n == 1'b0) begin
            S1_req_Concat <= 'd0;
        end else if(step[0] == 1'b1 && step[1] == 1'b0) begin
            S1_req_Concat <= ~(double_req_Concat - {4'b0,aribe_value});
        end else begin
            S1_req_Concat <= S1_req_Concat;
        end
    end

    // step.2  
    always @(posedge I_clk) begin
        if(I_Rst_n == 1'b0) begin
            S2_req_Concat <= 'd0;
        end else if(step[1] == 1'b1 && step[2] == 1'b0) begin
            S2_req_Concat <= (S1_req_Concat & double_req_Concat);
        end else begin
            S2_req_Concat <= S2_req_Concat;
        end
    end

    assign S3_req_Concat = ((S2_req_Concat[3:0])|(S2_req_Concat[7:4]));

    // aribe_value
    always @(posedge I_clk) begin
        if(I_Rst_n == 1'b0) begin
            aribe_value <= {3'b0,1'b1};
        end else if(aribe_value[3] == 1'b1 && step[0] == 1'b1 && step[1] == 1'b0) begin
            aribe_value <= {3'b0,1'b1};
        end else if(step[0] == 1'b1 && step[1] == 1'b0) begin
            aribe_value <= aribe_value << 1;
        end else begin
            aribe_value <= aribe_value;
        end
    end

    //req
    //ch0
    always @(posedge I_clk) begin
        if(I_Rst_n == 1'b0) begin
            reg_ch0_vaild <= 1'b0;
        end else if(state == state_ch0_0 && (r1_ch0_start == 1'b1 && r2_ch0_start == 1'b0)) begin
            reg_ch0_vaild <= 1'b0;
        end else if(state == state_ch0_0 && reg_ch0_vaild == 1'b0) begin
            reg_ch0_vaild <= 1'b1;
        end
    end
    //ch1
    always @(posedge I_clk) begin
        if(I_Rst_n == 1'b0) begin
            reg_ch1_vaild <= 1'b0;
        end else if(state == state_ch1_0 && (r1_ch1_start == 1'b1 && r2_ch1_start == 1'b0)) begin
            reg_ch1_vaild <= 1'b0;
        end else if(state == state_ch1_0 && reg_ch1_vaild == 1'b0) begin
            reg_ch1_vaild <= 1'b1;
        end
    end
    //ch2
    always @(posedge I_clk) begin
        if(I_Rst_n == 1'b0) begin
            reg_ch2_vaild <= 1'b0;
        end else if(state == state_ch2_0 && (r1_ch2_start == 1'b1 && r2_ch2_start == 1'b0)) begin
            reg_ch2_vaild <= 1'b0;
        end else if(state == state_ch2_0 && reg_ch2_vaild == 1'b0) begin
            reg_ch2_vaild <= 1'b1;
        end
    end
    //ch3
    always @(posedge I_clk) begin
        if(I_Rst_n == 1'b0) begin
            reg_ch3_vaild <= 1'b0;
        end else if(state == state_ch3_0 && (r1_ch3_start == 1'b1 && r2_ch3_start == 1'b0)) begin
            reg_ch3_vaild <= 1'b0;
        end else if(state == state_ch3_0 && reg_ch3_vaild == 1'b0) begin
            reg_ch3_vaild <= 1'b1;
        end
    end

    //state
    always @(posedge I_clk) begin
        if(I_Rst_n == 1'b0) begin
            state <= state_idle;
        end else begin
            case (state)
                state_idle: begin
                    if(aribe_start == 1'b1 && aribe_cycle == 1'b0) begin
                        state <= state_aribe;
                    end else begin
                        state <= state_idle;
                    end
                end
                state_aribe:begin
                    if(step[2] == 1'b1 && step[3] == 1'b0) begin
                        case (S3_req_Concat)
                            4'b0001:begin
                                state <= state_ch0_0;
                            end 
                            4'b0010:begin
                                state <= state_ch1_0;
                            end 
                            4'b0100:begin
                                state <= state_ch2_0;
                            end 
                            4'b1000:begin
                                state <= state_ch3_0;
                            end 
                            default: state <= state_aribe;
                        endcase
                    end else begin
                        state <= state_aribe;
                    end
                end
                // state.step.0
                state_ch0_0:begin
                    if((r1_ch0_start == 1'b1 && r2_ch0_start == 1'b0)) begin
                        state <= state_ch0_1;
                    end else begin
                        state <= state_ch0_0;
                    end
                end
                state_ch1_0:begin
                    if((r1_ch1_start == 1'b1 && r2_ch1_start == 1'b0)) begin
                        state <= state_ch1_1;
                    end else begin
                        state <= state_ch1_0;
                    end
                end
                state_ch2_0:begin
                    if((r1_ch2_start == 1'b1 && r2_ch2_start == 1'b0)) begin
                        state <= state_ch2_1;
                    end else begin
                        state <= state_ch2_0;
                    end
                end
                state_ch3_0:begin
                    if((r1_ch3_start == 1'b1 && r2_ch3_start == 1'b0)) begin
                        state <= state_ch3_1;
                    end else begin
                        state <= state_ch3_0;
                    end
                end

                // state.step.1
                state_ch0_1:begin
                    if(I_ch0_end == 1'b1) begin
                        state <= state_idle;
                    end else begin
                        state <= state_ch0_1;
                    end
                end
                state_ch1_1:begin
                    if(I_ch1_end == 1'b1) begin
                        state <= state_idle;
                    end else begin
                        state <= state_ch1_1;
                    end
                end
                state_ch2_1:begin
                    if(I_ch2_end == 1'b1) begin
                        state <= state_idle;
                    end else begin
                        state <= state_ch2_1;
                    end
                end
                state_ch3_1:begin
                    if(I_ch3_end == 1'b1) begin
                        state <= state_idle;
                    end else begin
                        state <= state_ch3_1;
                    end
                end
                default: begin
                    state <= state_idle;
                end
            endcase
        end
    end  
    always @(*) begin
        if(state == state_ch0_0||state == state_ch0_1) begin
            M_AXI_ARID        <= CH0_M_AXI_ARID     ;
            M_AXI_ARADDR      <= CH0_M_AXI_ARADDR   ;
            M_AXI_ARLEN       <= CH0_M_AXI_ARLEN    ;
            M_AXI_ARSIZE      <= CH0_M_AXI_ARSIZE   ;
            M_AXI_ARBURST     <= CH0_M_AXI_ARBURST  ;
            M_AXI_ARLOCK      <= CH0_M_AXI_ARLOCK   ;
            M_AXI_ARCACHE     <= CH0_M_AXI_ARCACHE  ;
            M_AXI_ARPROT      <= CH0_M_AXI_ARPROT   ;
            M_AXI_ARQOS       <= CH0_M_AXI_ARQOS    ;
            M_AXI_ARUSER      <= CH0_M_AXI_ARUSER   ;
            M_AXI_ARVALID     <= CH0_M_AXI_ARVALID  ;
            CH0_M_AXI_ARREADY <= M_AXI_ARREADY      ;

            CH0_M_AXI_RID     <= M_AXI_RID          ;
            CH0_M_AXI_RDATA   <= M_AXI_RDATA        ;
            CH0_M_AXI_RRESP   <= M_AXI_RRESP        ;
            CH0_M_AXI_RLAST   <= M_AXI_RLAST        ;
            CH0_M_AXI_RUSER   <= M_AXI_RUSER        ;
            CH0_M_AXI_RVALID  <= M_AXI_RVALID       ;
            M_AXI_RREADY      <= CH0_M_AXI_RREADY   ;
        end else if(state == state_ch1_0 || state == state_ch1_1) begin
            M_AXI_ARID        <= CH1_M_AXI_ARID     ;
            M_AXI_ARADDR      <= CH1_M_AXI_ARADDR   ;
            M_AXI_ARLEN       <= CH1_M_AXI_ARLEN    ;
            M_AXI_ARSIZE      <= CH1_M_AXI_ARSIZE   ;
            M_AXI_ARBURST     <= CH1_M_AXI_ARBURST  ;
            M_AXI_ARLOCK      <= CH1_M_AXI_ARLOCK   ;
            M_AXI_ARCACHE     <= CH1_M_AXI_ARCACHE  ;
            M_AXI_ARPROT      <= CH1_M_AXI_ARPROT   ;
            M_AXI_ARQOS       <= CH1_M_AXI_ARQOS    ;
            M_AXI_ARUSER      <= CH1_M_AXI_ARUSER   ;
            M_AXI_ARVALID     <= CH1_M_AXI_ARVALID  ;
            CH1_M_AXI_ARREADY <= M_AXI_ARREADY      ;

            CH1_M_AXI_RID     <= M_AXI_RID          ;
            CH1_M_AXI_RDATA   <= M_AXI_RDATA        ;
            CH1_M_AXI_RRESP   <= M_AXI_RRESP        ;
            CH1_M_AXI_RLAST   <= M_AXI_RLAST        ;
            CH1_M_AXI_RUSER   <= M_AXI_RUSER        ;
            CH1_M_AXI_RVALID  <= M_AXI_RVALID       ;
            M_AXI_RREADY      <= CH1_M_AXI_RREADY   ;
        end else if(state == state_ch2_0 || state == state_ch2_1) begin
            M_AXI_ARID        <= CH2_M_AXI_ARID     ;
            M_AXI_ARADDR      <= CH2_M_AXI_ARADDR   ;
            M_AXI_ARLEN       <= CH2_M_AXI_ARLEN    ;
            M_AXI_ARSIZE      <= CH2_M_AXI_ARSIZE   ;
            M_AXI_ARBURST     <= CH2_M_AXI_ARBURST  ;
            M_AXI_ARLOCK      <= CH2_M_AXI_ARLOCK   ;
            M_AXI_ARCACHE     <= CH2_M_AXI_ARCACHE  ;
            M_AXI_ARPROT      <= CH2_M_AXI_ARPROT   ;
            M_AXI_ARQOS       <= CH2_M_AXI_ARQOS    ;
            M_AXI_ARUSER      <= CH2_M_AXI_ARUSER   ;
            M_AXI_ARVALID     <= CH2_M_AXI_ARVALID  ;
            CH2_M_AXI_ARREADY <= M_AXI_ARREADY      ;

            CH2_M_AXI_RID     <= M_AXI_RID          ;
            CH2_M_AXI_RDATA   <= M_AXI_RDATA        ;
            CH2_M_AXI_RRESP   <= M_AXI_RRESP        ;
            CH2_M_AXI_RLAST   <= M_AXI_RLAST        ;
            CH2_M_AXI_RUSER   <= M_AXI_RUSER        ;
            CH2_M_AXI_RVALID  <= M_AXI_RVALID       ;
            M_AXI_RREADY      <= CH2_M_AXI_RREADY   ;
        end else if(state == state_ch3_0 || state == state_ch3_1) begin
            M_AXI_ARID        <= CH3_M_AXI_ARID     ;
            M_AXI_ARADDR      <= CH3_M_AXI_ARADDR   ;
            M_AXI_ARLEN       <= CH3_M_AXI_ARLEN    ;
            M_AXI_ARSIZE      <= CH3_M_AXI_ARSIZE   ;
            M_AXI_ARBURST     <= CH3_M_AXI_ARBURST  ;
            M_AXI_ARLOCK      <= CH3_M_AXI_ARLOCK   ;
            M_AXI_ARCACHE     <= CH3_M_AXI_ARCACHE  ;
            M_AXI_ARPROT      <= CH3_M_AXI_ARPROT   ;
            M_AXI_ARQOS       <= CH3_M_AXI_ARQOS    ;
            M_AXI_ARUSER      <= CH3_M_AXI_ARUSER   ;
            M_AXI_ARVALID     <= CH3_M_AXI_ARVALID  ;
            CH3_M_AXI_ARREADY <= M_AXI_ARREADY      ;

            CH3_M_AXI_RID     <= M_AXI_RID          ;
            CH3_M_AXI_RDATA   <= M_AXI_RDATA        ;
            CH3_M_AXI_RRESP   <= M_AXI_RRESP        ;
            CH3_M_AXI_RLAST   <= M_AXI_RLAST        ;
            CH3_M_AXI_RUSER   <= M_AXI_RUSER        ;
            CH3_M_AXI_RVALID  <= M_AXI_RVALID       ;
            M_AXI_RREADY      <= CH3_M_AXI_RREADY   ;
        end else begin
            M_AXI_ARID        <= CH3_M_AXI_ARID     ;
            M_AXI_ARADDR      <= CH3_M_AXI_ARADDR   ;
            M_AXI_ARLEN       <= CH3_M_AXI_ARLEN    ;
            M_AXI_ARSIZE      <= CH3_M_AXI_ARSIZE   ;
            M_AXI_ARBURST     <= CH3_M_AXI_ARBURST  ;
            M_AXI_ARLOCK      <= CH3_M_AXI_ARLOCK   ;
            M_AXI_ARCACHE     <= CH3_M_AXI_ARCACHE  ;
            M_AXI_ARPROT      <= CH3_M_AXI_ARPROT   ;
            M_AXI_ARQOS       <= CH3_M_AXI_ARQOS    ;
            M_AXI_ARUSER      <= CH3_M_AXI_ARUSER   ;
            M_AXI_ARVALID     <= CH3_M_AXI_ARVALID  ;
            CH3_M_AXI_ARREADY <= M_AXI_ARREADY      ;

            CH3_M_AXI_RID     <= M_AXI_RID          ;
            CH3_M_AXI_RDATA   <= M_AXI_RDATA        ;
            CH3_M_AXI_RRESP   <= M_AXI_RRESP        ;
            CH3_M_AXI_RLAST   <= M_AXI_RLAST        ;
            CH3_M_AXI_RUSER   <= M_AXI_RUSER        ;
            CH3_M_AXI_RVALID  <= M_AXI_RVALID       ;
            M_AXI_RREADY      <= CH3_M_AXI_RREADY   ;
        end
    end
endmodule

寫

module  Aribe_state_wr #(
        parameter integer M_AXI_ID_WIDTH                    = 1          ,
        parameter integer M_AXI_ADDR_WIDTH                  = 32         ,
        parameter integer M_AXI_DATA_WIDTH                  = 64         ,
        parameter integer M_AXI_AWUSER_WIDTH                = 0          ,
        parameter integer M_AXI_ARUSER_WIDTH                = 0          ,
        parameter integer M_AXI_WUSER_WIDTH                 = 0          ,
        parameter integer M_AXI_RUSER_WIDTH                 = 0          ,
        parameter integer M_AXI_BUSER_WIDTH                 = 0             
    )(
        input    wire                              I_clk         ,
        input    wire                              I_Rst_n       ,
        //Port                 
        //ch0                  
        input    wire                              I_ch0_req     ,
        input    wire                              I_ch0_start   ,
        input    wire                              I_ch0_end     ,
        output   wire                              O_ch0_vaild   ,
        //ch1                  
        input    wire                              I_ch1_req     ,
        input    wire                              I_ch1_start   ,
        input    wire                              I_ch1_end     ,
        output   wire                              O_ch1_vaild   ,
        //ch2                  
        input    wire                              I_ch2_req     ,
        input    wire                              I_ch2_start   ,
        input    wire                              I_ch2_end     ,
        output   wire                              O_ch2_vaild   ,
        //ch3                  
        input    wire                              I_ch3_req     ,
        input    wire                              I_ch3_start   ,
        input    wire                              I_ch3_end     ,
        output   wire                              O_ch3_vaild   ,
    //CH0
        input    wire [M_AXI_ID_WIDTH-1 : 0]       CH0_M_AXI_AWID    ,
        input    wire [M_AXI_ADDR_WIDTH-1 : 0]     CH0_M_AXI_AWADDR  ,
        input    wire [7 : 0]                      CH0_M_AXI_AWLEN   ,
        input    wire [2 : 0]                      CH0_M_AXI_AWSIZE  ,
        input    wire [1 : 0]                      CH0_M_AXI_AWBURST ,
        input    wire                              CH0_M_AXI_AWLOCK  ,
        input    wire [3 : 0]                      CH0_M_AXI_AWCACHE ,
        input    wire [2 : 0]                      CH0_M_AXI_AWPROT  ,
        input    wire [3 : 0]                      CH0_M_AXI_AWQOS   ,
        input    wire [M_AXI_AWUSER_WIDTH-1 : 0]   CH0_M_AXI_AWUSER  ,
        input    wire                              CH0_M_AXI_AWVALID ,
        output   reg                               CH0_M_AXI_AWREADY ,

        input    wire [M_AXI_DATA_WIDTH-1 : 0]     CH0_M_AXI_WDATA   ,
        input    wire [M_AXI_DATA_WIDTH/8-1 : 0]   CH0_M_AXI_WSTRB   ,
        input    wire                              CH0_M_AXI_WLAST   ,
        input    wire [M_AXI_WUSER_WIDTH-1 : 0]    CH0_M_AXI_WUSER   ,
        input    wire                              CH0_M_AXI_WVALID  ,
        output   reg                               CH0_M_AXI_WREADY  ,

        output   reg  [M_AXI_ID_WIDTH-1 : 0]       CH0_M_AXI_BID     ,
        output   reg  [1 : 0]                      CH0_M_AXI_BRESP   ,
        output   reg  [M_AXI_BUSER_WIDTH-1 : 0]    CH0_M_AXI_BUSER   ,
        output   reg                               CH0_M_AXI_BVALID  ,
        input    wire                              CH0_M_AXI_BREADY  ,
    //CH1
        input    wire [M_AXI_ID_WIDTH-1 : 0]       CH1_M_AXI_AWID    ,
        input    wire [M_AXI_ADDR_WIDTH-1 : 0]     CH1_M_AXI_AWADDR  ,
        input    wire [7 : 0]                      CH1_M_AXI_AWLEN   ,
        input    wire [2 : 0]                      CH1_M_AXI_AWSIZE  ,
        input    wire [1 : 0]                      CH1_M_AXI_AWBURST ,
        input    wire                              CH1_M_AXI_AWLOCK  ,
        input    wire [3 : 0]                      CH1_M_AXI_AWCACHE ,
        input    wire [2 : 0]                      CH1_M_AXI_AWPROT  ,
        input    wire [3 : 0]                      CH1_M_AXI_AWQOS   ,
        input    wire [M_AXI_AWUSER_WIDTH-1 : 0]   CH1_M_AXI_AWUSER  ,
        input    wire                              CH1_M_AXI_AWVALID ,
        output   reg                               CH1_M_AXI_AWREADY ,

        input    wire [M_AXI_DATA_WIDTH-1 : 0]     CH1_M_AXI_WDATA   ,
        input    wire [M_AXI_DATA_WIDTH/8-1 : 0]   CH1_M_AXI_WSTRB   ,
        input    wire                              CH1_M_AXI_WLAST   ,
        input    wire [M_AXI_WUSER_WIDTH-1 : 0]    CH1_M_AXI_WUSER   ,
        input    wire                              CH1_M_AXI_WVALID  ,
        output   reg                               CH1_M_AXI_WREADY  ,

        output   reg  [M_AXI_ID_WIDTH-1 : 0]       CH1_M_AXI_BID     ,
        output   reg  [1 : 0]                      CH1_M_AXI_BRESP   ,
        output   reg  [M_AXI_BUSER_WIDTH-1 : 0]    CH1_M_AXI_BUSER   ,
        output   reg                               CH1_M_AXI_BVALID  ,
        input    wire                              CH1_M_AXI_BREADY  ,
    //CH2
        input    wire [M_AXI_ID_WIDTH-1 : 0]       CH2_M_AXI_AWID    ,
        input    wire [M_AXI_ADDR_WIDTH-1 : 0]     CH2_M_AXI_AWADDR  ,
        input    wire [7 : 0]                      CH2_M_AXI_AWLEN   ,
        input    wire [2 : 0]                      CH2_M_AXI_AWSIZE  ,
        input    wire [1 : 0]                      CH2_M_AXI_AWBURST ,
        input    wire                              CH2_M_AXI_AWLOCK  ,
        input    wire [3 : 0]                      CH2_M_AXI_AWCACHE ,
        input    wire [2 : 0]                      CH2_M_AXI_AWPROT  ,
        input    wire [3 : 0]                      CH2_M_AXI_AWQOS   ,
        input    wire [M_AXI_AWUSER_WIDTH-1 : 0]   CH2_M_AXI_AWUSER  ,
        input    wire                              CH2_M_AXI_AWVALID ,
        output   reg                               CH2_M_AXI_AWREADY ,

        input    wire [M_AXI_DATA_WIDTH-1 : 0]     CH2_M_AXI_WDATA   ,
        input    wire [M_AXI_DATA_WIDTH/8-1 : 0]   CH2_M_AXI_WSTRB   ,
        input    wire                              CH2_M_AXI_WLAST   ,
        input    wire [M_AXI_WUSER_WIDTH-1 : 0]    CH2_M_AXI_WUSER   ,
        input    wire                              CH2_M_AXI_WVALID  ,
        output   reg                               CH2_M_AXI_WREADY  ,

        output   reg  [M_AXI_ID_WIDTH-1 : 0]       CH2_M_AXI_BID     ,
        output   reg  [1 : 0]                      CH2_M_AXI_BRESP   ,
        output   reg  [M_AXI_BUSER_WIDTH-1 : 0]    CH2_M_AXI_BUSER   ,
        output   reg                               CH2_M_AXI_BVALID  ,
        input    wire                              CH2_M_AXI_BREADY  ,
    //CH3
        input    wire [M_AXI_ID_WIDTH-1 : 0]       CH3_M_AXI_AWID    ,
        input    wire [M_AXI_ADDR_WIDTH-1 : 0]     CH3_M_AXI_AWADDR  ,
        input    wire [7 : 0]                      CH3_M_AXI_AWLEN   ,
        input    wire [2 : 0]                      CH3_M_AXI_AWSIZE  ,
        input    wire [1 : 0]                      CH3_M_AXI_AWBURST ,
        input    wire                              CH3_M_AXI_AWLOCK  ,
        input    wire [3 : 0]                      CH3_M_AXI_AWCACHE ,
        input    wire [2 : 0]                      CH3_M_AXI_AWPROT  ,
        input    wire [3 : 0]                      CH3_M_AXI_AWQOS   ,
        input    wire [M_AXI_AWUSER_WIDTH-1 : 0]   CH3_M_AXI_AWUSER  ,
        input    wire                              CH3_M_AXI_AWVALID ,
        output   reg                               CH3_M_AXI_AWREADY ,

        input    wire [M_AXI_DATA_WIDTH-1 : 0]     CH3_M_AXI_WDATA   ,
        input    wire [M_AXI_DATA_WIDTH/8-1 : 0]   CH3_M_AXI_WSTRB   ,
        input    wire                              CH3_M_AXI_WLAST   ,
        input    wire [M_AXI_WUSER_WIDTH-1 : 0]    CH3_M_AXI_WUSER   ,
        input    wire                              CH3_M_AXI_WVALID  ,
        output   reg                               CH3_M_AXI_WREADY  ,

        output   reg  [M_AXI_ID_WIDTH-1 : 0]       CH3_M_AXI_BID     ,
        output   reg  [1 : 0]                      CH3_M_AXI_BRESP   ,
        output   reg  [M_AXI_BUSER_WIDTH-1 : 0]    CH3_M_AXI_BUSER   ,
        output   reg                               CH3_M_AXI_BVALID  ,
        input    wire                              CH3_M_AXI_BREADY  ,
    //result
        output   reg  [M_AXI_ID_WIDTH-1 : 0]       M_AXI_AWID    ,
        output   reg  [M_AXI_ADDR_WIDTH-1 : 0]     M_AXI_AWADDR  ,
        output   reg  [7 : 0]                      M_AXI_AWLEN   ,
        output   reg  [2 : 0]                      M_AXI_AWSIZE  ,
        output   reg  [1 : 0]                      M_AXI_AWBURST ,
        output   reg                               M_AXI_AWLOCK  ,
        output   reg  [3 : 0]                      M_AXI_AWCACHE ,
        output   reg  [2 : 0]                      M_AXI_AWPROT  ,
        output   reg  [3 : 0]                      M_AXI_AWQOS   ,
        output   reg  [M_AXI_AWUSER_WIDTH-1 : 0]   M_AXI_AWUSER  ,
        output   reg                               M_AXI_AWVALID ,
        input    wire                              M_AXI_AWREADY ,

        output   reg  [M_AXI_DATA_WIDTH-1 : 0]     M_AXI_WDATA   ,
        output   reg  [M_AXI_DATA_WIDTH/8-1 : 0]   M_AXI_WSTRB   ,
        output   reg                               M_AXI_WLAST   ,
        output   reg  [M_AXI_WUSER_WIDTH-1 : 0]    M_AXI_WUSER   ,
        output   reg                               M_AXI_WVALID  ,
        input    wire                              M_AXI_WREADY  ,

        input    wire [M_AXI_ID_WIDTH-1 : 0]       M_AXI_BID     ,
        input    wire [1 : 0]                      M_AXI_BRESP   ,
        input    wire [M_AXI_BUSER_WIDTH-1 : 0]    M_AXI_BUSER   ,
        input    wire                              M_AXI_BVALID  ,
        output   reg                               M_AXI_BREADY  
);

    //-----------------------------------------------------------------//
        localparam  state_idle  = 10'b0000_0000_01;
        localparam  state_aribe = 10'b0000_0000_10;

        localparam  state_ch0_0 = 10'b0000_0001_00;
        localparam  state_ch0_1 = 10'b0000_0010_00;

        localparam  state_ch1_0 = 10'b0000_0100_00;
        localparam  state_ch1_1 = 10'b0000_1000_00;

        localparam  state_ch2_0 = 10'b0001_0000_00;
        localparam  state_ch2_1 = 10'b0010_0000_00;

        localparam  state_ch3_0 = 10'b0100_0000_00;
        localparam  state_ch3_1 = 10'b1000_0000_00;

    //-----------------------------------------------------------------//
        //req
            //step.0
            wire    [3:0]   single_req_Concat           ;
            reg     [7:0]   double_req_Concat           ;
            //step.1
            reg     [7:0]   S1_req_Concat               ;
            //step.2
            reg     [7:0]   S2_req_Concat               ;
            //step.3
            wire    [3:0]   S3_req_Concat               ;
        //aribe
            wire            aribe_start                 ;
            wire            aribe_step                  ;
            reg             aribe_cycle                 ;
            reg     [3:0]   aribe_value                 ;
        //step
            reg     [3:0]   step                        ;
        //state
            reg     [9:0]   state                       ;
            wire            aribe_ch0_end               ;
            wire            aribe_ch1_end               ;
            wire            aribe_ch2_end               ;
            wire            aribe_ch3_end               ;
        //req vaild
            reg             reg_ch0_vaild               ;
            reg             reg_ch1_vaild               ;
            reg             reg_ch2_vaild               ;
            reg             reg_ch3_vaild               ;
        //start
            reg             r1_ch0_start                ;
            reg             r2_ch0_start                ;

            reg             r1_ch1_start                ;
            reg             r2_ch1_start                ;

            reg             r1_ch2_start                ;
            reg             r2_ch2_start                ;

            reg             r1_ch3_start                ;
            reg             r2_ch3_start                ;
    //-----------------------------------------------------------------//
    assign  single_req_Concat = {I_ch3_req, I_ch2_req, I_ch1_req, I_ch0_req};
    assign  aribe_start  = |single_req_Concat;
    assign  aribe_step   = (aribe_start == 1'b1 && aribe_cycle == 1'b0);

    assign  aribe_ch0_end = (I_ch0_end == 1'b1)&&(state == state_ch0_1);
    assign  aribe_ch1_end = (I_ch1_end == 1'b1)&&(state == state_ch1_1);
    assign  aribe_ch2_end = (I_ch2_end == 1'b1)&&(state == state_ch2_1);
    assign  aribe_ch3_end = (I_ch3_end == 1'b1)&&(state == state_ch3_1);

    assign O_ch0_vaild  = reg_ch0_vaild;
    assign O_ch1_vaild  = reg_ch1_vaild;
    assign O_ch2_vaild  = reg_ch2_vaild;
    assign O_ch3_vaild  = reg_ch3_vaild;

    always @(posedge I_clk) begin
        step[3:0] <= {step[2:0],aribe_step};
    end

    // Pose
    always @(posedge I_clk) begin
        {r2_ch0_start,r1_ch0_start} <= {r1_ch0_start,I_ch0_start};
        {r2_ch1_start,r1_ch1_start} <= {r1_ch1_start,I_ch1_start};
        {r2_ch2_start,r1_ch2_start} <= {r1_ch2_start,I_ch2_start};
        {r2_ch3_start,r1_ch3_start} <= {r1_ch3_start,I_ch3_start};
    end

    // aribe_cycle
    always @(posedge I_clk) begin
        if(I_Rst_n == 1'b0) begin
            aribe_cycle <= 1'b0;
        end else if(aribe_ch0_end|aribe_ch1_end|aribe_ch2_end|aribe_ch3_end) begin
            aribe_cycle <= 1'b0;
        end else if(aribe_start == 1'b1 && aribe_cycle == 1'b0 && state == state_idle) begin
            aribe_cycle <= 1'b1;
        end else begin
            aribe_cycle <= aribe_cycle;
        end
    end

    // step.0
    always @(posedge I_clk) begin
        if(I_Rst_n == 1'b0) begin
            double_req_Concat <= 'd0;
        end else if(aribe_step == 1'b1 && step[0] == 1'b0) begin
            double_req_Concat <= {2{I_ch3_req, I_ch2_req, I_ch1_req, I_ch0_req}};
        end else begin
            double_req_Concat <= double_req_Concat;
        end
    end

    // step.1
    always @(posedge I_clk) begin
        if(I_Rst_n == 1'b0) begin
            S1_req_Concat <= 'd0;
        end else if(step[0] == 1'b1 && step[1] == 1'b0) begin
            S1_req_Concat <= ~(double_req_Concat - {4'b0,aribe_value});
        end else begin
            S1_req_Concat <= S1_req_Concat;
        end
    end

    // step.2  
    always @(posedge I_clk) begin
        if(I_Rst_n == 1'b0) begin
            S2_req_Concat <= 'd0;
        end else if(step[1] == 1'b1 && step[2] == 1'b0) begin
            S2_req_Concat <= (S1_req_Concat & double_req_Concat);
        end else begin
            S2_req_Concat <= S2_req_Concat;
        end
    end

    assign S3_req_Concat = ((S2_req_Concat[3:0])|(S2_req_Concat[7:4]));

    // aribe_value
    always @(posedge I_clk) begin
        if(I_Rst_n == 1'b0) begin
            aribe_value <= {3'b0,1'b1};
        end else if(aribe_value[3] == 1'b1 && step[0] == 1'b1 && step[1] == 1'b0) begin
            aribe_value <= {3'b0,1'b1};
        end else if(step[0] == 1'b1 && step[1] == 1'b0) begin
            aribe_value <= aribe_value << 1;
        end else begin
            aribe_value <= aribe_value;
        end
    end

    //req
    //ch0
    always @(posedge I_clk) begin
        if(I_Rst_n == 1'b0) begin
            reg_ch0_vaild <= 1'b0;
        end else if(state == state_ch0_0 && (r1_ch0_start == 1'b1 && r2_ch0_start == 1'b0)) begin
            reg_ch0_vaild <= 1'b0;
        end else if(state == state_ch0_0 && reg_ch0_vaild == 1'b0) begin
            reg_ch0_vaild <= 1'b1;
        end
    end
    //ch1
    always @(posedge I_clk) begin
        if(I_Rst_n == 1'b0) begin
            reg_ch1_vaild <= 1'b0;
        end else if(state == state_ch1_0 && (r1_ch1_start == 1'b1 && r2_ch1_start == 1'b0)) begin
            reg_ch1_vaild <= 1'b0;
        end else if(state == state_ch1_0 && reg_ch1_vaild == 1'b0) begin
            reg_ch1_vaild <= 1'b1;
        end
    end
    //ch2
    always @(posedge I_clk) begin
        if(I_Rst_n == 1'b0) begin
            reg_ch2_vaild <= 1'b0;
        end else if(state == state_ch2_0 && (r1_ch2_start == 1'b1 && r2_ch2_start == 1'b0)) begin
            reg_ch2_vaild <= 1'b0;
        end else if(state == state_ch2_0 && reg_ch2_vaild == 1'b0) begin
            reg_ch2_vaild <= 1'b1;
        end
    end
    //ch3
    always @(posedge I_clk) begin
        if(I_Rst_n == 1'b0) begin
            reg_ch3_vaild <= 1'b0;
        end else if(state == state_ch3_0 && (r1_ch3_start == 1'b1 && r2_ch3_start == 1'b0)) begin
            reg_ch3_vaild <= 1'b0;
        end else if(state == state_ch3_0 && reg_ch3_vaild == 1'b0) begin
            reg_ch3_vaild <= 1'b1;
        end
    end

    //state
    always @(posedge I_clk) begin
        if(I_Rst_n == 1'b0) begin
            state <= state_idle;
        end else begin
            case (state)
                state_idle: begin
                    if(aribe_start == 1'b1 && aribe_cycle == 1'b0) begin
                        state <= state_aribe;
                    end else begin
                        state <= state_idle;
                    end
                end
                state_aribe:begin
                    if(step[2] == 1'b1 && step[3] == 1'b0) begin
                        case (S3_req_Concat)
                            4'b0001:begin
                                state <= state_ch0_0;
                            end 
                            4'b0010:begin
                                state <= state_ch1_0;
                            end 
                            4'b0100:begin
                                state <= state_ch2_0;
                            end 
                            4'b1000:begin
                                state <= state_ch3_0;
                            end 
                            default: state <= state_aribe;
                        endcase
                    end else begin
                        state <= state_aribe;
                    end
                end
                // state.step.0
                state_ch0_0:begin
                    if((r1_ch0_start == 1'b1 && r2_ch0_start == 1'b0)) begin
                        state <= state_ch0_1;
                    end else begin
                        state <= state_ch0_0;
                    end
                end
                state_ch1_0:begin
                    if((r1_ch1_start == 1'b1 && r2_ch1_start == 1'b0)) begin
                        state <= state_ch1_1;
                    end else begin
                        state <= state_ch1_0;
                    end
                end
                state_ch2_0:begin
                    if((r1_ch2_start == 1'b1 && r2_ch2_start == 1'b0)) begin
                        state <= state_ch2_1;
                    end else begin
                        state <= state_ch2_0;
                    end
                end
                state_ch3_0:begin
                    if((r1_ch3_start == 1'b1 && r2_ch3_start == 1'b0)) begin
                        state <= state_ch3_1;
                    end else begin
                        state <= state_ch3_0;
                    end
                end

                // state.step.1
                state_ch0_1:begin
                    if(I_ch0_end == 1'b1) begin
                        state <= state_idle;
                    end else begin
                        state <= state_ch0_1;
                    end
                end
                state_ch1_1:begin
                    if(I_ch1_end == 1'b1) begin
                        state <= state_idle;
                    end else begin
                        state <= state_ch1_1;
                    end
                end
                state_ch2_1:begin
                    if(I_ch2_end == 1'b1) begin
                        state <= state_idle;
                    end else begin
                        state <= state_ch2_1;
                    end
                end
                state_ch3_1:begin
                    if(I_ch3_end == 1'b1) begin
                        state <= state_idle;
                    end else begin
                        state <= state_ch3_1;
                    end
                end
                default: begin
                    state <= state_idle;
                end
            endcase
        end
    end  

    always @(*) begin
        if(state == state_ch0_0||state == state_ch0_1) begin
            M_AXI_AWID        <= CH0_M_AXI_AWID   ;
            M_AXI_AWADDR      <= CH0_M_AXI_AWADDR ;
            M_AXI_AWLEN       <= CH0_M_AXI_AWLEN  ;
            M_AXI_AWSIZE      <= CH0_M_AXI_AWSIZE ;
            M_AXI_AWBURST     <= CH0_M_AXI_AWBURST;
            M_AXI_AWLOCK      <= CH0_M_AXI_AWLOCK ;
            M_AXI_AWCACHE     <= CH0_M_AXI_AWCACHE;
            M_AXI_AWPROT      <= CH0_M_AXI_AWPROT ;
            M_AXI_AWQOS       <= CH0_M_AXI_AWQOS  ;
            M_AXI_AWUSER      <= CH0_M_AXI_AWUSER ;
            M_AXI_AWVALID     <= CH0_M_AXI_AWVALID;
            CH0_M_AXI_AWREADY <= M_AXI_AWREADY    ;
            M_AXI_WDATA       <= CH0_M_AXI_WDATA  ;
            M_AXI_WSTRB       <= CH0_M_AXI_WSTRB  ;
            M_AXI_WLAST       <= CH0_M_AXI_WLAST  ;
            M_AXI_WUSER       <= CH0_M_AXI_WUSER  ;
            M_AXI_WVALID      <= CH0_M_AXI_WVALID ;
            CH0_M_AXI_WREADY  <= M_AXI_WREADY     ;
            CH0_M_AXI_BID     <= M_AXI_BID        ;
            CH0_M_AXI_BRESP   <= M_AXI_BRESP      ;
            CH0_M_AXI_BUSER   <= M_AXI_BUSER      ;
            CH0_M_AXI_BVALID  <= M_AXI_BVALID     ;
            M_AXI_BREADY      <= CH0_M_AXI_BREADY ;
        end else if(state == state_ch1_0 || state == state_ch1_1) begin
            M_AXI_AWID        <= CH1_M_AXI_AWID   ;
            M_AXI_AWADDR      <= CH1_M_AXI_AWADDR ;
            M_AXI_AWLEN       <= CH1_M_AXI_AWLEN  ;
            M_AXI_AWSIZE      <= CH1_M_AXI_AWSIZE ;
            M_AXI_AWBURST     <= CH1_M_AXI_AWBURST;
            M_AXI_AWLOCK      <= CH1_M_AXI_AWLOCK ;
            M_AXI_AWCACHE     <= CH1_M_AXI_AWCACHE;
            M_AXI_AWPROT      <= CH1_M_AXI_AWPROT ;
            M_AXI_AWQOS       <= CH1_M_AXI_AWQOS  ;
            M_AXI_AWUSER      <= CH1_M_AXI_AWUSER ;
            M_AXI_AWVALID     <= CH1_M_AXI_AWVALID;
            CH1_M_AXI_AWREADY <= M_AXI_AWREADY    ;
            M_AXI_WDATA       <= CH1_M_AXI_WDATA  ;
            M_AXI_WSTRB       <= CH1_M_AXI_WSTRB  ;
            M_AXI_WLAST       <= CH1_M_AXI_WLAST  ;
            M_AXI_WUSER       <= CH1_M_AXI_WUSER  ;
            M_AXI_WVALID      <= CH1_M_AXI_WVALID ;
            CH1_M_AXI_WREADY  <= M_AXI_WREADY     ;
            CH1_M_AXI_BID     <= M_AXI_BID        ;
            CH1_M_AXI_BRESP   <= M_AXI_BRESP      ;
            CH1_M_AXI_BUSER   <= M_AXI_BUSER      ;
            CH1_M_AXI_BVALID  <= M_AXI_BVALID     ;
            M_AXI_BREADY      <= CH1_M_AXI_BREADY ;
        end else if(state == state_ch2_0 || state == state_ch2_1) begin
            M_AXI_AWID        <= CH2_M_AXI_AWID   ;
            M_AXI_AWADDR      <= CH2_M_AXI_AWADDR ;
            M_AXI_AWLEN       <= CH2_M_AXI_AWLEN  ;
            M_AXI_AWSIZE      <= CH2_M_AXI_AWSIZE ;
            M_AXI_AWBURST     <= CH2_M_AXI_AWBURST;
            M_AXI_AWLOCK      <= CH2_M_AXI_AWLOCK ;
            M_AXI_AWCACHE     <= CH2_M_AXI_AWCACHE;
            M_AXI_AWPROT      <= CH2_M_AXI_AWPROT ;
            M_AXI_AWQOS       <= CH2_M_AXI_AWQOS  ;
            M_AXI_AWUSER      <= CH2_M_AXI_AWUSER ;
            M_AXI_AWVALID     <= CH2_M_AXI_AWVALID;
            CH2_M_AXI_AWREADY <= M_AXI_AWREADY    ;
            M_AXI_WDATA       <= CH2_M_AXI_WDATA  ;
            M_AXI_WSTRB       <= CH2_M_AXI_WSTRB  ;
            M_AXI_WLAST       <= CH2_M_AXI_WLAST  ;
            M_AXI_WUSER       <= CH2_M_AXI_WUSER  ;
            M_AXI_WVALID      <= CH2_M_AXI_WVALID ;
            CH2_M_AXI_WREADY  <= M_AXI_WREADY     ;
            CH2_M_AXI_BID     <= M_AXI_BID        ;
            CH2_M_AXI_BRESP   <= M_AXI_BRESP      ;
            CH2_M_AXI_BUSER   <= M_AXI_BUSER      ;
            CH2_M_AXI_BVALID  <= M_AXI_BVALID     ;
            M_AXI_BREADY      <= CH2_M_AXI_BREADY ;
        end else if(state == state_ch3_0 || state == state_ch3_1) begin
            M_AXI_AWID        <= CH3_M_AXI_AWID   ;
            M_AXI_AWADDR      <= CH3_M_AXI_AWADDR ;
            M_AXI_AWLEN       <= CH3_M_AXI_AWLEN  ;
            M_AXI_AWSIZE      <= CH3_M_AXI_AWSIZE ;
            M_AXI_AWBURST     <= CH3_M_AXI_AWBURST;
            M_AXI_AWLOCK      <= CH3_M_AXI_AWLOCK ;
            M_AXI_AWCACHE     <= CH3_M_AXI_AWCACHE;
            M_AXI_AWPROT      <= CH3_M_AXI_AWPROT ;
            M_AXI_AWQOS       <= CH3_M_AXI_AWQOS  ;
            M_AXI_AWUSER      <= CH3_M_AXI_AWUSER ;
            M_AXI_AWVALID     <= CH3_M_AXI_AWVALID;
            CH3_M_AXI_AWREADY <= M_AXI_AWREADY    ;
            M_AXI_WDATA       <= CH3_M_AXI_WDATA  ;
            M_AXI_WSTRB       <= CH3_M_AXI_WSTRB  ;
            M_AXI_WLAST       <= CH3_M_AXI_WLAST  ;
            M_AXI_WUSER       <= CH3_M_AXI_WUSER  ;
            M_AXI_WVALID      <= CH3_M_AXI_WVALID ;
            CH3_M_AXI_WREADY  <= M_AXI_WREADY     ;
            CH3_M_AXI_BID     <= M_AXI_BID        ;
            CH3_M_AXI_BRESP   <= M_AXI_BRESP      ;
            CH3_M_AXI_BUSER   <= M_AXI_BUSER      ;
            CH3_M_AXI_BVALID  <= M_AXI_BVALID     ;
            M_AXI_BREADY      <= CH3_M_AXI_BREADY ;
        end else begin
            M_AXI_AWID        <= CH3_M_AXI_AWID   ;
            M_AXI_AWADDR      <= CH3_M_AXI_AWADDR ;
            M_AXI_AWLEN       <= CH3_M_AXI_AWLEN  ;
            M_AXI_AWSIZE      <= CH3_M_AXI_AWSIZE ;
            M_AXI_AWBURST     <= CH3_M_AXI_AWBURST;
            M_AXI_AWLOCK      <= CH3_M_AXI_AWLOCK ;
            M_AXI_AWCACHE     <= CH3_M_AXI_AWCACHE;
            M_AXI_AWPROT      <= CH3_M_AXI_AWPROT ;
            M_AXI_AWQOS       <= CH3_M_AXI_AWQOS  ;
            M_AXI_AWUSER      <= CH3_M_AXI_AWUSER ;
            M_AXI_AWVALID     <= CH3_M_AXI_AWVALID;
            CH3_M_AXI_AWREADY <= M_AXI_AWREADY    ;
            M_AXI_WDATA       <= CH3_M_AXI_WDATA  ;
            M_AXI_WSTRB       <= CH3_M_AXI_WSTRB  ;
            M_AXI_WLAST       <= CH3_M_AXI_WLAST  ;
            M_AXI_WUSER       <= CH3_M_AXI_WUSER  ;
            M_AXI_WVALID      <= CH3_M_AXI_WVALID ;
            CH3_M_AXI_WREADY  <= M_AXI_WREADY     ;
            CH3_M_AXI_BID     <= M_AXI_BID        ;
            CH3_M_AXI_BRESP   <= M_AXI_BRESP      ;
            CH3_M_AXI_BUSER   <= M_AXI_BUSER      ;
            CH3_M_AXI_BVALID  <= M_AXI_BVALID     ;
            M_AXI_BREADY      <= CH3_M_AXI_BREADY ;
        end
    end
endmodule

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