1. WHAT IS AXI?
AXI是一種高階可擴充套件介面，是ARM AMBA的一部分。
2. WHAT IS AMBA?
AMBA是高階微控制器匯流排架構，開放的片內互聯匯流排標準。
3．AXI分類
AXI4/AXI4_ITE/AXI4_STREAM
Memory_mapped 儲存器對映 就是讀寫資料時需要目標地址。
AXI4(AXI4_FULL):用於高效能儲存對映。例如：AXI4讀寫DDR3。
AXI4_LITE:簡單的，低吞吐率。比如說一些控制暫存器和狀態暫存器。
AXI4_STREAM（ST）：高速的流資料通訊。
AXI4(AXI4_FULL)和AXI4_LITE需要主機指定讀寫的地址。AXI4_STREAM（ST）屬於流資料，不需要儲存器對映不需要地址。
4.儲存器對映（Memory_mapped）
主機在對從機進行讀寫操作時，要先指定一個目標地址（target address），在這個地址對應系統儲存空間的地址，表示對該空間進行讀寫操作。
Memory-Mapped Protocols: In memory-mapped protocols (AXI3, AXI4, and
AXI4-Lite), all transactions involve the concept of transferring a target
address within a
system memory space and data.
AXI_Stream不屬於儲存器對映。
5.AXI4的優勢
AXI的優勢
生產力：
靈活性：AXI4（支援突發256）和AXI4_lite（不支援突發，1個資料）都屬於儲存器對映。AXI_ST不屬於儲存器對映，突發長度不受限制。
可獲得性：
6.what is 互聯？
7. five different channels
Both AXI4 and AXI4-Lite interfaces consist of five different channels:
• Read Address Channel
• Write Address Channel
• Read Data Channel
• Write Data Channel
• Write Response Channel
主機傳送讀地址，從機返回讀資料
Data can move in both directions between
the master and slave simultaneously, and data
transfer sizes can vary. The limit in AXI4 is a burst
transaction of up to 256 data transfers.
AXI4-Lite allows only one data transfer per
transaction.
讀操作：主機通過讀地址通道向從機發出地址和控制，從機通過讀資料通道傳送讀資料。根據突發長度大小返回不同個數的資料。
寫操作：主機先通過寫地址通道發出地址和控制訊號。然後通過寫資料通道發出資料，等從機接收到資料會傳送response訊號。
AXI4:
讀寫地址分離，支援同時讀寫。
需要一個單一地址然後進行256個資料突發。
As shown in the preceding figures, AXI4:
• Provides separate data and address connections for
reads and writes, which allows
simultaneous, bidirectional data transfer.
• Requires a single address and then bursts up to 256
words of data.
AXI4_LITE:
單次一個資料，不支援突發傳輸。
AXI4-Lite is similar to AXI4 with some
exceptions: The most notable exception is that
bursting is not supported.
AXI4-Stream：
單通道傳輸資料類似AXI4的寫資料通道，且寫資料大小沒有突發限制。
The AXI4-Stream protocol defines a single channel for
transmission of streaming data. The AXI4-Stream channel models the write data channel of AXI4.
Unlike AXI4, AXI4-Stream
interfaces can burst an unlimited amount of data.
只關心資料流，不需要地址。
AXI4-Stream
Protocol: Use the AXI4-Stream protocol for applications that typically
focus on a data-centric and data-flow paradigm where the concept of an address
is not
present or not required. Each AXI4-Stream acts as a single unidirectional
channel with a
handshaking data flow.
Infrastructure
IP: An infrastructure IP is a building block used to help assemble
systems. Infrastructure IP tends to be a generic IP that moves or transforms
data
around the system using general-purpose AXI4 interfaces and does not interpret
data.
Examples of infrastructure IP are:
° AXI Register slices (for pipelining)
° AXI FIFOs (for buffering/clock conversion)
° AXI Interconnect IP and AXI SmartConnect IP (for
connecting memory-mapped IP
together)
° AXI Direct Memory Access (DMA) engines (for memory-mapped
to stream
conversion)
° AXI Performance Monitors and Protocol Checkers
(for analysis and debug)
° AXI Verification IP (for simulation-based
verification and performance analysis)
These IP are useful for connecting IP together into a system, but are not
generally
endpoints for data.
DMA常用於儲存器對映和stream資料流的轉換。
比如說ddr中儲存了你的有效資料需要做fft fft IP的介面時stream流 ddr的資料是儲存器對映，做操作需要DMA做資料轉換。
A common
approach is to build systems that combine AXI4-Stream and AXI
memory-mapped IP together. Often a DMA engine can be used to move streams in
and out
of memory.
注意AXI Data width converter 和 AXI Direct Memory Access支援的AXI介面協議。
8.AXI SmartConnect IP and AXI Interconnect IP
兩者都用於一些主從裝置的互聯（儲存器對映型別）。在一些情況下, AXI SmartConnect IP可以提供高頻寬的連結以及低延遲。
The Xilinx LogiCORE IP AXI Interconnect and LogiCORE IP AXI SmartConnect cores both connect one or more AXI memory-mapped master devices to one or more memory-mapped slave devices; however, the SmartConnect is more tightly integrated into the Vivado design environment to automatically configure and adapt to connected AXI master and slave IP with minimal user intervention. The AXI Interconnect can be used in all memory-mapped designs. There are certain cases for high bandwidth application where using a SmartConnect provides better optimization. The AXI SmartConnect IP delivers the maximum system throughput at low latency by synthesizing a low area custom interconnect that is optimized for important interfaces.The AXI Interconnect core IP (axi_interconnect) connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices。
今天先到這裡。
參考資料：
IHI0022D
UG1037
正點原子ZYNQ嵌入式教程