第二版相較第一版：增加了仲裁和更多的引數化；
第三版相較第二版：統一輸入位寬，把位寬轉換模組放在外面明顯更方便；
轉來轉去的事情以後不在dma裡做了！
1 `timescale 1 ns / 1 ps 2 3 module dma_complex # 4 ( 5 parameter WR_Base_addr = 32'h2000000, 6 parameter RD_Base_addr = 32'h2000000, 7 parameter integer C_M_AXI_BURST_LEN = 256 , 8 parameter integer C_M_AXI_ID_WIDTH = 1 , 9 parameter integer C_M_AXI_ADDR_WIDTH = 32 , 10 parameter integer C_M_AXI_DATA_WIDTH = 64 , 11 parameter integer C_M_AXI_AWUSER_WIDTH = 0 , 12 parameter integer C_M_AXI_ARUSER_WIDTH = 0 , 13 parameter integer C_M_AXI_WUSER_WIDTH = 0 , 14 parameter integer C_M_AXI_RUSER_WIDTH = 0 , 15 parameter integer C_M_AXI_BUSER_WIDTH = 0 , 16 parameter I_image_w = 1920 , 17 parameter I_image_h = 1080 , 18 parameter Pixel_byte_num = 4 , 19 parameter AXI_Buff_NUM = 3 , 20 parameter WR_CH_EN = 1 , 21 parameter RD_CH_EN = 1 22 ) 23 ( 24 input wire M_AXI_ACLK , 25 input wire M_AXI_ARESETN , 26 output wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_AWID , 27 output wire [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_AWADDR , 28 output wire [7 : 0] M_AXI_AWLEN , 29 output wire [2 : 0] M_AXI_AWSIZE , 30 output wire [1 : 0] M_AXI_AWBURST , 31 output wire M_AXI_AWLOCK , 32 output wire [3 : 0] M_AXI_AWCACHE , 33 output wire [2 : 0] M_AXI_AWPROT , 34 output wire [3 : 0] M_AXI_AWQOS , 35 output wire [C_M_AXI_AWUSER_WIDTH-1 : 0] M_AXI_AWUSER , 36 output wire M_AXI_AWVALID , 37 input wire M_AXI_AWREADY , 38 39 output wire [C_M_AXI_DATA_WIDTH-1 : 0] M_AXI_WDATA , 40 output wire [C_M_AXI_DATA_WIDTH/8-1 : 0] M_AXI_WSTRB , 41 output wire M_AXI_WLAST , 42 output wire [C_M_AXI_WUSER_WIDTH-1 : 0] M_AXI_WUSER , 43 output wire M_AXI_WVALID , 44 input wire M_AXI_WREADY , 45 46 input wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_BID , 47 input wire [1 : 0] M_AXI_BRESP , 48 input wire [C_M_AXI_BUSER_WIDTH-1 : 0] M_AXI_BUSER , 49 input wire M_AXI_BVALID , 50 output wire M_AXI_BREADY , 51 52 output wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_ARID , 53 output wire [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_ARADDR , 54 output wire [7 : 0] M_AXI_ARLEN , 55 output wire [2 : 0] M_AXI_ARSIZE , 56 output wire [1 : 0] M_AXI_ARBURST , 57 output wire M_AXI_ARLOCK , 58 output wire [3 : 0] M_AXI_ARCACHE , 59 output wire [2 : 0] M_AXI_ARPROT , 60 output wire [3 : 0] M_AXI_ARQOS , 61 output wire [C_M_AXI_ARUSER_WIDTH-1 : 0] M_AXI_ARUSER , 62 output wire M_AXI_ARVALID , 63 input wire M_AXI_ARREADY , 64 65 input wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_RID , 66 input wire [C_M_AXI_DATA_WIDTH-1 : 0] M_AXI_RDATA , 67 input wire [1 : 0] M_AXI_RRESP , 68 input wire M_AXI_RLAST , 69 input wire [C_M_AXI_RUSER_WIDTH-1 : 0] M_AXI_RUSER , 70 input wire M_AXI_RVALID , 71 output wire M_AXI_RREADY , 72 73 //Custom 74 input wire [7:0] I_wr_index ,// 僅讀通道下接受所讀取幀的位置； 75 input wire I_rd_start , 76 //Aribe-----------------------------------------------------// 77 output wire O_wr_req , 78 input wire I_Aribe_wr_enable , 79 output wire O_wr_brust_start , 80 output wire O_wr_brust_end , 81 82 output wire O_rd_req , 83 input wire I_Aribe_rd_enable , 84 output wire O_rd_brust_start , 85 output wire O_rd_brust_end , 86 //Aribe-----------------------------------------------------// 87 input wire I_Pre_clk , 88 input wire I_Pre_vs , 89 input wire [C_M_AXI_DATA_WIDTH -1:0] I_Pre_data , 90 input wire I_Pre_de , 91 output wire [7:0] O_wr_index , 92 93 input wire I_Post_clk , 94 output wire O_Post_Start ,//Reset Post Module 95 output wire [C_M_AXI_DATA_WIDTH -1:0] O_Post_data , 96 input wire I_Post_de 97 ); 98 99 function integer clogb2 (input integer bit_depth); 100 begin 101 for(clogb2=0; bit_depth>0; clogb2=clogb2+1) 102 bit_depth = bit_depth >> 1; 103 end 104 endfunction 105 106 //========================================= Define Ports =========================================// 107 localparam integer C_TRANSACTIONS_NUM = clogb2(C_M_AXI_BURST_LEN-1) ; 108 109 localparam Awaddr_Brust_Offset = (C_M_AXI_DATA_WIDTH)*(C_M_AXI_BURST_LEN)/8 ; 110 localparam Araddr_Brust_Offset = (C_M_AXI_DATA_WIDTH)*(C_M_AXI_BURST_LEN)/8 ; 111 localparam Total_Frame_Offset = I_image_w*I_image_h*Pixel_byte_num ; 112 localparam RAM_1_start_addr = 0 ; 113 localparam RAM_2_start_addr = Total_Frame_Offset ; 114 localparam RAM_3_start_addr = Total_Frame_Offset*2 ; 115 116 localparam wr_burst_times = I_image_w*I_image_h*Pixel_byte_num /Awaddr_Brust_Offset ; 117 localparam rd_burst_times = I_image_w*I_image_h*Pixel_byte_num /Araddr_Brust_Offset ; 118 119 //========================================= Define Ports =========================================// 120 121 // AXI4LITE signals 122 //AXI4 internal temp signals 123 reg [C_M_AXI_ADDR_WIDTH-1 : 0] axi_awaddr ; 124 reg axi_awvalid ; 125 126 reg axi_wlast ; 127 reg axi_wvalid ; 128 reg [C_TRANSACTIONS_NUM-1:0] wr_burst_cnt ; 129 130 reg axi_bready ; 131 132 reg [C_M_AXI_ADDR_WIDTH-1 : 0] axi_araddr ; 133 reg axi_arvalid ; 134 reg axi_rready ; 135 136 //W_FIFO 137 wire wr_fifo_wr_en ; 138 wire [C_M_AXI_DATA_WIDTH-1 : 0] wr_fifo_wr_data ; 139 wire wr_fifo_rd_en ; 140 wire [C_M_AXI_DATA_WIDTH-1 : 0] wr_fifo_rd_data ; 141 wire full_w ; 142 wire empty_w ; 143 wire [15 : 0] w_rd_data_count ; 144 wire [15 : 0] w_wr_data_count ; 145 146 //r_FIFO 147 wire rd_fifo_wr_en ; 148 wire [C_M_AXI_DATA_WIDTH-1 : 0] rd_fifo_wr_data ; 149 150 wire rd_fifo_rd_en ; 151 wire [C_M_AXI_DATA_WIDTH-1 : 0] rd_fifo_rd_data ; 152 153 wire [15 : 0] r_rd_data_count ; 154 wire [15 : 0] r_wr_data_count ; 155 wire full_r ; 156 wire empty_r ; 157 158 reg [15:0] rd_hcnt ; 159 reg [15:0] rd_vcnt ; 160 161 //I/O Connections. Write Address (AW) 162 assign M_AXI_AWID = 'b0; 163 assign M_AXI_AWADDR = WR_Base_addr + axi_awaddr; 164 assign M_AXI_AWLEN = C_M_AXI_BURST_LEN - 1; 165 assign M_AXI_AWSIZE = clogb2((C_M_AXI_DATA_WIDTH/8)-1); 166 assign M_AXI_AWBURST = 2'b01; 167 assign M_AXI_AWLOCK = 1'b0; 168 assign M_AXI_AWCACHE = 4'b0010; 169 assign M_AXI_AWPROT = 3'h0; 170 assign M_AXI_AWQOS = 4'h0; 171 assign M_AXI_AWUSER = 'b1; 172 assign M_AXI_AWVALID = axi_awvalid; 173 //Write Data(W) 174 assign wr_fifo_rd_en = (axi_wvalid == 1'b1)&&(M_AXI_WREADY == 1'b1); 175 assign M_AXI_WDATA = wr_fifo_rd_data; 176 //All bursts are complete and aligned in this example 177 assign M_AXI_WSTRB = {(C_M_AXI_DATA_WIDTH/8){1'b1}}; 178 assign M_AXI_WLAST = axi_wlast; 179 assign M_AXI_WUSER = 'b0; 180 assign M_AXI_WVALID = axi_wvalid; 181 //Write Response (B) 182 assign M_AXI_BREADY = axi_bready; 183 //Read Address (AR) 184 assign M_AXI_ARID = 'b0; 185 assign M_AXI_ARADDR = RD_Base_addr + axi_araddr; 186 assign M_AXI_ARLEN = C_M_AXI_BURST_LEN - 1; 187 assign M_AXI_ARSIZE = clogb2((C_M_AXI_DATA_WIDTH/8)-1); 188 assign M_AXI_ARBURST = 2'b01; 189 assign M_AXI_ARLOCK = 1'b0; 190 assign M_AXI_ARCACHE = 4'b0010; 191 assign M_AXI_ARPROT = 3'h0; 192 assign M_AXI_ARQOS = 4'h0; 193 assign M_AXI_ARUSER = 'b1; 194 assign M_AXI_ARVALID = axi_arvalid; 195 //Read and Read Response (R) 196 assign M_AXI_RREADY = axi_rready; 197 198 // Wr_Sync------------------------------------------------------------------------------------------// 199 200 //W Sync Port 201 //wrclk 202 reg r1_pre_vs ; 203 wire Pose_pre_vs ; 204 wire Nege_pre_vs ; 205 wire Ext_Pose_pre_vs ; 206 //sysclk 207 reg sys_pre_vs ; 208 reg r1_sys_pre_vs ; 209 reg sys_Pose_pre_vs ; 210 reg sys_Nege_pre_vs ; 211 reg r_sys_Nege_pre_vs; 212 reg [1:0] wr_index ; 213 reg [C_M_AXI_ADDR_WIDTH-1 : 0] wr_base_addr ; 214 215 always @(posedge I_Pre_clk) begin 216 r1_pre_vs <= I_Pre_vs; 217 end 218 219 assign Pose_pre_vs = (I_Pre_vs == 1'b1)&&(r1_pre_vs == 1'b0); 220 assign Nege_pre_vs = (I_Pre_vs == 1'b0)&&(r1_pre_vs == 1'b1); 221 222 always@(posedge M_AXI_ACLK) begin 223 sys_pre_vs <= I_Pre_vs ; 224 r1_sys_pre_vs <= sys_pre_vs; 225 r_sys_Nege_pre_vs <= sys_Nege_pre_vs; 226 end 227 228 always @(posedge M_AXI_ACLK) begin 229 if(M_AXI_ARESETN == 1'b0) begin 230 sys_Pose_pre_vs <= 1'b0; 231 sys_Nege_pre_vs <= 1'b0; 232 end else if(sys_pre_vs==1'b1&&r1_sys_pre_vs==1'b0) begin 233 sys_Pose_pre_vs <= 1'b1; 234 sys_Nege_pre_vs <= 1'b0; 235 end else if(sys_pre_vs==1'b0&&r1_sys_pre_vs==1'b1) begin 236 sys_Pose_pre_vs <= 1'b0; 237 sys_Nege_pre_vs <= 1'b1; 238 end else begin 239 sys_Pose_pre_vs <= 1'b0; 240 sys_Nege_pre_vs <= 1'b0; 241 end 242 end 243 244 245 Data_sync_ext Data_sync_ext_Inst0( 246 .clka ( I_Pre_clk ), 247 .rst_n ( M_AXI_ARESETN ), 248 .pulse_a ( Pose_pre_vs ), 249 .ext_pulse_a ( Ext_Pose_pre_vs ) 250 ); 251 252 always@(posedge M_AXI_ACLK) 253 if(M_AXI_ARESETN == 1'b0) begin 254 wr_index <= 'd1; 255 end else if(sys_Nege_pre_vs == 1'b1&&wr_index == AXI_Buff_NUM) begin 256 wr_index <= 'd1; 257 end else if(sys_Nege_pre_vs==1'b1) begin 258 wr_index <= wr_index + 1'b1; 259 end else begin 260 wr_index <= wr_index; 261 end 262 263 assign O_wr_index = wr_index; 264 265 always@(posedge M_AXI_ACLK) 266 if(M_AXI_ARESETN == 1'b0) begin 267 wr_base_addr <= 0; 268 end else if(sys_Nege_pre_vs == 1'b1&&wr_index == AXI_Buff_NUM) begin 269 wr_base_addr <= 0; 270 end else if(sys_Nege_pre_vs == 1'b1) begin 271 wr_base_addr <= wr_base_addr + Total_Frame_Offset; 272 end else begin 273 wr_base_addr <= wr_base_addr; 274 end 275 276 // Wr_Sync------------------------------------------------------------------------------------------// 277 278 assign wr_fifo_wr_en = I_Pre_de; 279 assign wr_fifo_wr_data = I_Pre_data; 280 281 generate 282 if (WR_CH_EN[0]==1) begin: WR_EN 283 wdata_w256x256_r256x256 wdata_w256x256_r256x256 ( 284 .rst ( (!M_AXI_ARESETN)|(Ext_Pose_pre_vs)), // input wire rst 285 .wr_clk ( I_Pre_clk ), // input wire wr_clk 286 .rd_clk ( M_AXI_ACLK ), // input wire rd_clk 287 .din ( wr_fifo_wr_data ), // input wire [255 : 0] din 288 .wr_en ( wr_fifo_wr_en ), // input wire wr_en 289 .rd_en ( wr_fifo_rd_en ), // input wire rd_en 290 .dout ( wr_fifo_rd_data ), // output wire [255 : 0] dout 291 .full ( full_w ), // output wire full 292 .empty ( empty_w ), // output wire empty 293 .rd_data_count(w_rd_data_count ), // output wire [10 : 0] rd_data_count 294 .wr_data_count(w_wr_data_count ), // output wire [10 : 0] wr_data_count 295 .wr_rst_busy(), // output wire wr_rst_busy 296 .rd_rst_busy() // output wire rd_rst_busy 297 ); 298 end 299 endgenerate 300 301 // w_start_control----------------------------------------------------------------------------------// 302 303 //Control 304 reg wr_brust_start ; 305 wire wr_brust_Req ; 306 reg wr_brust_end ; 307 reg wr_brust_now ; 308 309 assign wr_brust_Req = (w_rd_data_count>=C_M_AXI_BURST_LEN); 310 assign O_wr_req = wr_brust_Req; 311 assign O_wr_brust_start = (wr_brust_start == 1'b1 && wr_brust_now == 1'b0); 312 assign O_wr_brust_end = wr_brust_end; 313 314 // 多路輸入的時候，wr_burst_Req輸出到仲裁器中，使用仲裁器輸出的aribe_req請求完成此處wr_burst_Req的工作 315 // 如果FIFO內資料滿足寫入需求：拉高請求 316 // 如果請求得到仲裁透過，啟動burst 317 always@(*) 318 if(WR_CH_EN[0] == 1'b1 && wr_brust_Req == 1'b1 && I_Aribe_wr_enable == 1'b1) begin 319 wr_brust_start <= 1'b1; 320 end else begin 321 wr_brust_start <= 1'b0; 322 end 323 324 always@(posedge M_AXI_ACLK) 325 if(M_AXI_ARESETN == 1'b0) begin 326 wr_brust_now <= 1'b0; 327 end else if(wr_brust_end == 1'b1 && wr_brust_now == 1'b1) begin 328 wr_brust_now <= 1'b0; 329 end else if(wr_brust_start == 1'b1 && wr_brust_now == 1'b0) begin 330 wr_brust_now <= 1'b1; 331 end else begin 332 wr_brust_now <= wr_brust_now; 333 end 334 335 always@(posedge M_AXI_ACLK) 336 if(M_AXI_ARESETN == 1'b0) begin 337 wr_brust_end <= 1'b0; 338 end else if(axi_wvalid==1'b1&&M_AXI_WREADY==1'b1&&wr_burst_cnt==C_M_AXI_BURST_LEN-1) begin 339 wr_brust_end <= 1'b1; 340 end else begin 341 wr_brust_end <= 1'b0; 342 end 343 344 // w_start_control----------------------------------------------------------------------------------// 345 346 // Aw------ --------------------------------------------------------------------------------------// 347 348 //axi_awvalid 349 always@(posedge M_AXI_ACLK) 350 if(M_AXI_ARESETN == 1'b0) begin 351 axi_awvalid <= 1'b0; 352 end else if(axi_awvalid == 1'b1 && M_AXI_AWREADY == 1'b1) begin 353 axi_awvalid <= 1'b0; 354 end else if(wr_brust_start == 1'b1 && wr_brust_now == 1'b0) begin 355 axi_awvalid <= 1'b1; 356 end else begin 357 axi_awvalid <= axi_awvalid; 358 end 359 360 //axi_awaddr 361 always@(posedge M_AXI_ACLK) 362 if(M_AXI_ARESETN == 1'b0) begin 363 axi_awaddr <= 'd0; 364 end else if(r_sys_Nege_pre_vs == 1'b1) begin 365 axi_awaddr <= wr_base_addr; 366 // end else if(r_sys_Nege_pre_vs == 1'b1) begin 367 // axi_awaddr <= 0; 368 end else if(axi_awvalid==1'b1 && M_AXI_AWREADY==1'b1) begin 369 axi_awaddr <= axi_awaddr + Awaddr_Brust_Offset ; 370 end else begin 371 axi_awaddr <= axi_awaddr; 372 end 373 374 // Aw---------------------------------------------------------------------------------------------// 375 376 // W----------------------------------------------------------------------------------------------// 377 //axi_wvalid 378 always@(posedge M_AXI_ACLK) 379 if(M_AXI_ARESETN == 1'b0) begin 380 axi_wvalid <= 1'b0; 381 end else if(axi_wvalid==1'b1&&M_AXI_WREADY==1'b1&&wr_burst_cnt==C_M_AXI_BURST_LEN-1) begin 382 axi_wvalid <= 1'b0; 383 end else if(axi_awvalid==1'b1&&M_AXI_AWREADY==1'b1) begin 384 axi_wvalid <= 1'b1; 385 end else begin 386 axi_wvalid <= axi_wvalid; 387 end 388 389 //wr_burst_cnt 390 always@(posedge M_AXI_ACLK) begin 391 if(M_AXI_ARESETN == 1'b0) begin 392 wr_burst_cnt <= 'd0; 393 end else if(axi_wvalid==1'b1&&M_AXI_WREADY==1'b1&&wr_burst_cnt==C_M_AXI_BURST_LEN-1) begin 394 wr_burst_cnt <= 'd0; 395 end else if(axi_wvalid==1'b1&&M_AXI_WREADY==1'b1) begin 396 wr_burst_cnt <= wr_burst_cnt + 1'b1; 397 end else begin 398 wr_burst_cnt <= wr_burst_cnt; 399 end 400 end 401 402 //axi_wlast 403 always@(posedge M_AXI_ACLK) begin 404 if(M_AXI_ARESETN == 1'b0) begin 405 axi_wlast <= 1'b0; 406 end else if(axi_wvalid==1'b1&&M_AXI_WREADY==1'b1&&wr_burst_cnt==C_M_AXI_BURST_LEN-1'b1) begin 407 axi_wlast <= 1'b0; 408 end else if(axi_wvalid==1'b1&&M_AXI_WREADY==1'b1&&wr_burst_cnt==C_M_AXI_BURST_LEN-2'd2) begin 409 axi_wlast <= 1'b1; 410 end else begin 411 axi_wlast <= axi_wlast; 412 end 413 end 414 415 // W----------------------------------------------------------------------------------------------// 416 417 // b----------------------------------------------------------------------------------------------// 418 419 always @(posedge M_AXI_ACLK) begin 420 if(M_AXI_ARESETN == 0) begin 421 axi_bready <= 'd0; 422 end else begin 423 axi_bready <= 1'b1; 424 end 425 end 426 427 // b----------------------------------------------------------------------------------------------// 428 429 // r_start_control----------------------------------------------------------------------------------// 430 431 //Control 432 reg [7:0] rd_index ; 433 reg [7:0] rd_index_ptr ; 434 reg [C_M_AXI_ADDR_WIDTH-1 : 0] rd_base_addr ; 435 436 reg rd_start_cycle ; 437 reg [2:0] rd_start_cnt ; 438 reg rd_brust_start ; 439 reg rd_brust_Req ; 440 reg rd_brust_end ; 441 reg rd_brust_now ; 442 reg Post_Start ; 443 444 always@(posedge M_AXI_ACLK) begin 445 if(M_AXI_ARESETN == 0) begin 446 rd_index <= 0; 447 end else case (WR_CH_EN[0] == 1'b1) 448 1'b0:begin 449 if(I_wr_index > 1) begin 450 rd_index <= I_wr_index - 1'b1; 451 end else begin 452 rd_index <= AXI_Buff_NUM; 453 end 454 end 455 1'b1:begin 456 if(wr_index > 1) begin 457 rd_index <= wr_index - 1'b1; 458 end else begin 459 rd_index <= AXI_Buff_NUM; 460 end 461 end 462 default: begin 463 rd_index <= rd_index; 464 end 465 endcase 466 end 467 468 always@(posedge M_AXI_ACLK) begin 469 if(M_AXI_ARESETN == 0) begin 470 rd_index_ptr <= 'd0; 471 end else begin 472 rd_index_ptr <= rd_index - 1'b1; 473 end 474 end 475 476 always@(posedge M_AXI_ACLK) begin 477 if(M_AXI_ARESETN == 0) begin 478 rd_base_addr <= 'd0; 479 end else begin 480 rd_base_addr <= rd_index_ptr*Total_Frame_Offset; 481 end 482 end 483 484 always@(posedge M_AXI_ACLK) begin 485 if(M_AXI_ARESETN == 0) begin 486 rd_start_cnt <= 'd0; 487 end else if(sys_Nege_pre_vs == 1'b1 && rd_start_cnt[2] != 1'b1 && WR_CH_EN[0] == 1'b1) begin 488 rd_start_cnt <= rd_start_cnt + 1'b1; 489 end else if(I_rd_start == 1'b1 && WR_CH_EN[0] == 1'b0) begin 490 rd_start_cnt <= rd_start_cnt + 1'b1; 491 end else begin 492 rd_start_cnt <= rd_start_cnt; 493 end 494 end 495 496 always@(posedge M_AXI_ACLK) begin 497 if(M_AXI_ARESETN == 0) begin 498 rd_start_cycle <= 1'b0; 499 end else if(rd_start_cnt[2] == 1'b1 && full_r == 1'b0) begin 500 rd_start_cycle <= 1'b1; 501 end else begin 502 rd_start_cycle <= rd_start_cycle; 503 end 504 end 505 506 always@(posedge I_Post_clk) 507 if(M_AXI_ARESETN == 0) begin 508 Post_Start <= 1'b0; 509 end else if(rd_start_cycle == 1'b1 && r_rd_data_count >= C_M_AXI_BURST_LEN) begin 510 Post_Start <= 1'b1; 511 end else begin 512 Post_Start <= Post_Start; 513 end 514 515 assign O_Post_Start = Post_Start ; 516 assign O_rd_req = rd_brust_Req; 517 assign O_rd_brust_start = (rd_brust_start == 1'b1 && rd_brust_now == 1'b0); 518 assign O_rd_brust_end = rd_brust_end; 519 520 521 always @(*) begin 522 if((RD_CH_EN[0] == 1'b1) && (rd_start_cycle == 1'b1) && (r_wr_data_count < C_M_AXI_BURST_LEN*4)) begin 523 rd_brust_Req <= 1'b1; 524 end else begin 525 rd_brust_Req <= 1'b0; 526 end 527 end 528 529 always@(posedge M_AXI_ACLK) 530 if(M_AXI_ARESETN == 1'b0) begin 531 rd_brust_end <= 1'b0; 532 end else if((M_AXI_RVALID == 1'b1)&&(axi_rready == 1'b1)&&(M_AXI_RLAST == 1'b1)) begin 533 rd_brust_end <= 1'b1; 534 end else begin 535 rd_brust_end <= 1'b0; 536 end 537 538 //No aribe 539 always@(*) begin 540 if(rd_brust_Req == 1'b1 && I_Aribe_rd_enable == 1'b1) begin 541 rd_brust_start <= 1'b1; 542 end else begin 543 rd_brust_start <= 1'b0; 544 end 545 end 546 547 always@(posedge M_AXI_ACLK) 548 if(M_AXI_ARESETN == 1'b0) begin 549 rd_brust_now <= 1'b0; 550 end else if(rd_brust_end == 1'b1 && rd_brust_now == 1'b1) begin 551 rd_brust_now <= 1'b0; 552 end else if(rd_brust_start == 1'b1 && rd_brust_now == 1'b0) begin 553 rd_brust_now <= 1'b1; 554 end else begin 555 rd_brust_now <= rd_brust_now; 556 end 557 558 // r_start_control----------------------------------------------------------------------------------// 559 560 // ar---------------------------------------------------------------------------------------------// 561 562 always@(posedge M_AXI_ACLK) begin 563 if(M_AXI_ARESETN == 1'b0) begin 564 axi_arvalid <= 1'b0; 565 end else if(axi_arvalid==1'b1&&M_AXI_ARREADY==1'b1) begin 566 axi_arvalid <= 1'b0; 567 end else if(rd_brust_start == 1'b1 && rd_brust_now == 1'b0) begin 568 axi_arvalid <= 1'b1; 569 end else begin 570 axi_arvalid <= axi_arvalid; 571 end 572 end 573 always@(posedge M_AXI_ACLK) begin 574 if(M_AXI_ARESETN == 1'b0) begin 575 axi_araddr <= 'd0; 576 end else if((M_AXI_RVALID == 1'b1)&&(axi_rready == 1'b1)&&(rd_hcnt == C_M_AXI_BURST_LEN - 1)&&(rd_vcnt == rd_burst_times - 1'b1)) begin 577 axi_araddr <= rd_base_addr; 578 end else if(axi_arvalid==1'b1&&M_AXI_ARREADY==1'b1) begin 579 axi_araddr <= axi_araddr + Araddr_Brust_Offset; 580 end else begin 581 axi_araddr <= axi_araddr; 582 end 583 end 584 // ar---------------------------------------------------------------------------------------------// 585 586 // r----------------------------------------------------------------------------------------------// 587 588 always@(posedge M_AXI_ACLK) begin 589 if(M_AXI_ARESETN == 1'b0) begin 590 axi_rready <= 1'b0; 591 end else if((M_AXI_RVALID == 1'b1)&&(axi_rready == 1'b1)&&(M_AXI_RLAST == 1'b1)) begin 592 axi_rready <= 1'b0; 593 end else if(axi_arvalid==1'b1&&M_AXI_ARREADY==1'b1) begin 594 axi_rready <= 1'b1; 595 end else begin 596 axi_rready <= axi_rready; 597 end 598 end 599 600 // r----------------------------------------------------------------------------------------------// 601 602 603 // r_Sync-----------------------------------------------------------------------------------------// 604 605 606 assign rd_fifo_wr_en = (M_AXI_RVALID == 1'b1)&&(axi_rready == 1'b1); 607 assign rd_fifo_wr_data = M_AXI_RDATA; 608 609 assign rd_fifo_rd_en = I_Post_de && Post_Start; 610 assign O_Post_data = rd_fifo_rd_data; 611 612 generate 613 if (RD_CH_EN[0]==1) begin: RD_EN 614 rdata_w256x512_r256x512 rdata_w256x512_r256x512 ( 615 .rst ( (!M_AXI_ARESETN)&&(!rd_start_cnt[2])), // input wire rst 616 .wr_clk ( M_AXI_ACLK ), // input wire wr_clk 617 .rd_clk ( I_Post_clk ), // input wire rd_clk 618 .din ( rd_fifo_wr_data ), // input wire [255 : 0] din 619 .wr_en ( rd_fifo_wr_en ), // input wire wr_en 620 .rd_en ( rd_fifo_rd_en ), // input wire rd_en 621 .dout ( rd_fifo_rd_data ), // output wire [255 : 0] dout 622 .full ( full_r ), // output wire full 623 .empty ( empty_r ), // output wire empty 624 .rd_data_count( r_rd_data_count ), // output wire [8 : 0] rd_data_count 625 .wr_data_count( r_wr_data_count ), // output wire [8 : 0] wr_data_count 626 .wr_rst_busy(), // output wire wr_rst_busy 627 .rd_rst_busy() // output wire rd_rst_busy 628 ); 629 end 630 endgenerate 631 632 //hcnt 633 always@(posedge M_AXI_ACLK)begin 634 if(M_AXI_ARESETN == 1'b0) begin 635 rd_hcnt <= 'd0; 636 end else if((M_AXI_RVALID == 1'b1)&&(axi_rready == 1'b1)&&(rd_hcnt == C_M_AXI_BURST_LEN - 1)) begin 637 rd_hcnt <= 'd0; 638 end else if((M_AXI_RVALID == 1'b1)&&(axi_rready == 1'b1)) begin 639 rd_hcnt <= rd_hcnt + 1'b1; 640 end else begin 641 rd_hcnt <= rd_hcnt; 642 end 643 end 644 //vcnt 645 always@(posedge M_AXI_ACLK)begin 646 if(M_AXI_ARESETN == 1'b0) begin 647 rd_vcnt <= 'd0; 648 end else if((M_AXI_RVALID == 1'b1)&&(axi_rready == 1'b1)&&(rd_hcnt == C_M_AXI_BURST_LEN - 1)&&(rd_vcnt == rd_burst_times - 1'b1)) begin 649 rd_vcnt <= 'd0; 650 end else if((M_AXI_RVALID == 1'b1)&&(axi_rready == 1'b1)&&(rd_hcnt == C_M_AXI_BURST_LEN - 1)) begin 651 rd_vcnt <= rd_vcnt + 1'b1; 652 end else begin 653 rd_vcnt <= rd_vcnt; 654 end 655 end 656 657 endmodule