SDRAM 不帶自動預充電寫操作

//不帶自動預充電寫操作
//tRCD = 20ns, 取30ns
//tWR = 1clk + 7.5ns
//tRP = 20ns, 取30ns
//tRAS(max) = 12_0000ns, tRAS(min) = 44ns
//tRC(min) = 66ns
//clk=50M Hz
//預充電 {CS_N,RAS_N,CAS_N,WE_N} = 4'b0010
//空命令 {CS_N,RAS_N,CAS_N,WE_N} = 4'b0111
//寫命令 {CS_N,RAS_N,CAS_N,WE_N} = 4'b0100
//啟用命令 {CS_N,RAS_N,CAS_N,WE_N} = 4'b0011
//BL = 4

module sdr_w_n_a(
clk,
rst,
w_en,
w_done,
w_SDR_CLK,
w_CKE,
w_CS_N,
w_RAS_N,
w_CAS_N,
w_WE_N,
w_BA,
w_SA,
w_DQM,
w_DQ
);
input clk,rst;
input w_en;

output w_done;
output w_SDR_CLK;
output w_CKE;
output w_CS_N;
output w_RAS_N;
output w_CAS_N;
output w_WE_N;
output [1:0] w_BA;
output [12:0] w_SA;
output [1:0] w_DQM;
output [15:0] w_DQ;

reg [3:0] w_cnt;
reg w_done;
reg w_CKE;
reg w_CS_N;
reg w_RAS_N;
reg w_CAS_N;
reg w_WE_N;
reg [12:0] w_SA;
reg [1:0] w_DQM;
reg [1:0] w_BA;
reg [15:0] w_DQ;

parameter row = 13'b0_0000_0000_0000; //行地址
parameter col = 9'b0_0000_0000; //列地址
parameter bank = 2'b00; //bank地址

//==============================================
//線性序列機
//==============================================

always@(posedge clk or negedge rst)
begin
if(!rst)
begin
w_CS_N <= 1'b0;
w_RAS_N <= 1'b1;
w_CAS_N <= 1'b1;
w_WE_N <= 1'b1;
w_CKE <= 1'b0;
w_done <= 1'b0;
end
else
begin
case(w_cnt)
  0:begin //Active
w_CS_N <= 1'b0;
w_RAS_N <= 1'b0;
w_CAS_N <= 1'b1;
w_WE_N <= 1'b1;
w_CKE <= 1'b1;
w_done <= 1'b0;
w_SA <= row;
w_BA <= bank;
end
  2:begin   //Write
w_CS_N <= 1'b0;
w_RAS_N <= 1'b1;
w_CAS_N <= 1'b0;
w_WE_N <= 1'b0;
w_CKE <= 1'b1;
w_done <= 1'b0;
w_DQM <= 1'b0;
w_SA <= col;
w_SA[10] <= 1'b0;
w_BA <= bank;
w_DQ <= 16'd0;
end
  3:begin //Nop
w_CS_N <= 1'b0;
w_RAS_N <= 1'b1;
w_CAS_N <= 1'b1;
w_WE_N <= 1'b1;
w_DQM <= 1'b0;
w_DQ <= 16'd1;
end
  4:begin     //Nop
w_CS_N <= 1'b0;
w_RAS_N <= 1'b1;
w_CAS_N <= 1'b1;
w_WE_N <= 1'b1;
w_DQM <= 1'b0;
w_DQ <= 16'd2;
end
  5:begin //Nop
w_CS_N <= 1'b0;
w_RAS_N <= 1'b1;
w_CAS_N <= 1'b1;
w_WE_N <= 1'b1;
w_DQM <= 1'b0;
w_DQ <= 16'd3;
end
  7:begin   //Precharge
w_CS_N <= 1'b0;
w_RAS_N <= 1'b0;
w_CAS_N <= 1'b1;
w_WE_N <= 1'b0;
w_CKE <= 1'b1;
w_done <= 1'b0;
w_SA[10] <= 1'b1;
w_BA <= bank;
end
  9:begin   //結束給Nop命令
w_CS_N <= 1'b0;
w_RAS_N <= 1'b1;
w_CAS_N <= 1'b1;
w_WE_N <= 1'b1;
w_CKE <= 1'b0;
w_done <= 1'b1;
end
  10:begin //結束給Nop命令
w_CS_N <= 1'b0;
w_RAS_N <= 1'b1;
w_CAS_N <= 1'b1;
w_WE_N <= 1'b1;
w_CKE <= 1'b0;
w_done <= 1'b1;
end
  default:begin     //其他給Nop命令
w_CS_N <= 1'b0;
w_RAS_N <= 1'b1;
w_CAS_N <= 1'b1;
w_WE_N <= 1'b1;
w_CKE <= 1'b1;
w_done <= 1'b0;
   end
  endcase
end
end

//==============================================
// 計數器
//==============================================

always@(posedge clk or negedge rst)
begin
if(!rst) w_cnt <= 4'd0;
else if(w_en & (!w_done))
begin
if(w_cnt == 4'd10) w_cnt <= 4'd0;
else w_cnt <= w_cnt + 4'd1;
end
else w_cnt <= w_cnt;

end

//==============================================
// SDR_CLK
//==============================================

assign w_SDR_CLK = ~clk; //相位相差180度

//==============================================

endmodule

SDRAM 不帶自動預充電寫操作

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