MT6625L資料手冊/datasheet設計資料

MT6625L Datasheet：

原文資料內容：

Digital Logic Characteristics：

MT6625L timing characteristics and interface protocols are shown here, including some general comments.

1. Timing Diagram Convention

   Figure 3-1 shows the conventions used with timing diagram throughout this document。

   

2. Rising/Falling Time Definit

   
   

3. Figure 3-2 shows the rising and falling timing diagram. The actual signal timing curve is related to the 

external load conditions. The operating conditions of digital logics can be seen in Table 3-6。

4.Protocals

There are 3 main interfaces for MT6625L.

---3-wire SPI: Generally used for all systems (BT/Wi-Fi/FM/GPS)

---6-wire bus: High-speed interface, especially for BT and Wi-Fi

---FM 2-wire: Utilized as a simplified interface modified from I2S. This interface also defines MT6625L strap-pin modes. Do not add pull-up/pull-down to this interface. Failing to follow this recommendation will lead to unexpected MT6625L operation。

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