說明
新設計了1個KU040 FPGA板子，回來之後接上JTAG FPGA不識別。做如下檢查：
1、電源測試點均正常；
2、檢視貼片是否有漏焊，檢查無異常，設計上NC的才NC；
3、反覆檢查JTAG接線是否異常，貼片是否異常；
上述檢查均無問題，開始檢視原理圖，逐個對照XILINX手冊進行研究。
其中發現 CFGBVS 在設計圖中接了地，對照XILINX 手冊 https://www.amd.com/content/dam/xilinx/support/documents/user_guides/ug570-ultrascale-configuration.pdf
In the Kintex UltraScale and Virtex UltraScale FPGAs, the configuration banks voltage select
(CFGBVS) pin must be set to High or Low to determine the I/O voltage support for the pins
in bank 0, and for the multi-function pins in bank 65 when they are used during
configuration. The CFGBVS is a logic input pin referenced between VCCO_0 and GND. When
the CFGBVS pin is connected to the VCCO_0 supply of 3.3V or 2.5V, the configuration I/O
support operation at 3.3V or 2.5V. When the CFGBVS pin is connected to GND, the
configuration I/O support operation at 1.8V or 1.5V. There is no CFGBVS pin in the Artix
UltraScale+, Kintex UltraScale+, and Virtex UltraScale+ FPGAs because their configuration
I/O only support operation at 1.8V or 1.5V.
Configuration is not supported below the minimum recommended operating voltage for
1.5V as specified in the data sheet. The CFGBVS pin setting determines the I/O voltage
support for bank 0 at all times, before, during, and after configuration. CFGBVS similarly
controls the voltage tolerance on bank 65, but only during configuration.
也就是說，這裡原理圖 CFGBVS 接地肯定是不對的，必須拉高到3.3V，還好留了1個0歐姆電阻在這裡 還可以飛線補救一下。