Centaur: A Framework for Hybrid CPU-FPGA Databases
摘要
- Most existing work
- focused on either accelerating a single operator (e.g., a join)
- in data reduction along the data path (e.g., from disk to CPU)
啥叫data reduction啊???
- we focus
- the system aspects of
- accelerating a relational engine in hybrid CPU-FPGA architectures
- Centaur
- a framework running on the FPGA
- allows
- dynamic allocation of FPGA operators to query plans
- pipelining these operators among themselves when needed
- 在這些運算元之間還搞起了流水化呀?
- the hybrid execution of operator pipelines running on the CPU and the FPGA
- compatible with
- relational engines
- as we demonstrate through its seamless integration with MonetDB
- a column store database
- how this integration is achieved
- demonstrate the advantages of such an approach
- a realistic solution for accelerating SQL
- compatible with existing database architectures
- the possibilities for further exploration of FPGA based data processing
INTRODUCTION
-
the scope of operators and data types in relational databases is limited
-
The operators are defined by SQL
- the data can only be stored in basic and well defined data types
-
database engines are able to highly optimize the operator implementations for each data type
and CPU architecture. -
most database operators have
- low computational complexity
-
the rise in data sizes leads to new challenges and opportunities
- complex analytics operations
- ML
- statistics
- 圖分析
- traditional databases
- not perform well on these complex operators and data types
- accelerators offer an alternative way
- implement such complex functionality in databases
- how to integrate an accelerator like an FPGA in a database engine
2段
- Databases are throughput oriented,
- processing thousands to several hundred thousand queries per second.
- the type of operators potentially offloaded to the FPGA are
constantly changing.
資料庫是以吞吐量為中心的哦!!!
- database engine should
- be able to
- run hybrid queries combining FPGA and CPU operators
- in any order to harness the benefits of
- both FPGA accelerators and highly optimized CPU operators
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