PCIe Tandem PROM 方法

FPGA發表於2022-03-27

PCIe Tandem PROM 方法

什麼是Tandem PROM？

簡單總結：市面多數的FPGA都是SRAM型，需要在上電時從外部儲存器件完成程式碼的載入，對於具有PCIe功能的SRAM FPGA而言，必須要能夠在規定的100ms(PCIe Spec規定，實際上多數計算機要求不會這麼嚴格)時間內完成韌體的載入，此時計算機才能夠正確的列舉PCIe裝置並分配對應的地址。100ms的時間對SPI FLASH而言是個很大的挑戰，尤其是在FPGA SIZE越來越大時，為了解決這個問題，Xilinx為自己家的FPGA裝置提出了Tandem Configuration的概念，核心思想是將FPGA韌體分成2個部分，第一部分是PCIe部分，只負責PCIe的正常列舉，第二部分為使用者邏輯。顯然，這個技術需要FPGA廠商的支援，因此本文的Tandem專指Xilinx。

​ "PCI Express is a plug-and-play protocol meaning that at power up, the PCIe Host will enumerate the system. This process consists of the host reading the requested address size from each device and then assigning a base address to the device. As such, PCIe interfaces must be ready when the host queries them or they will not get assigned a base address. The PCI Express specification states that PERST# must deassert 100 ms after the power good of the systems has occurred, and a PCI Express port must be ready to link train no more than 20 ms after PERST# has deasserted. This is commonly referred to as the 100 ms boot time requirement. "

Tandem 有幾種方式？

實際使用中，Tandem PROM最為簡單，Tandem PCIe由於允許通過PCIe進行重配置，因此在伺服器領域最為常用(在其它需要經常更新韌體的場景下也適用)。本文只介紹Tandem PROM方式。

Tandem Configuration utilizes a two-stage methodology that enables the IP to meet the configuration time requirements indicated in the PCI Express specification. Multiple use cases are supported with this technology:

  • Tandem PROM: Load the single two-stage bitstream from the flash.
  • Tandem PCIe: Load the first stage bitstream from flash, and deliver the second stage bitstream over the PCIe link to the MCAP.
  • Tandem with Field Updates: After a Tandem PROM or Tandem PCIe initial configuration, update the entire user design while the PCIe link remains active. The update region (floorplan) and design structure are predefined, and Tcl scripts are provided.
  • Tandem + Partial Reconfiguration: This is a more general case of Tandem Configuration followed by Partial Reconfiguration (PR) of any size or number of PR regions.
  • Partial Reconfiguration over PCIe: This is a standard configuration followed by PR, using the PCIe / MCAP as the delivery path of partial bitstreams.

如何實現Tandem PROM？

本文介紹使用XDMA實現：

  • 在xdma配置時選擇advance mode，並選擇Tandem模式；

  • 然後右鍵選擇生成example_design，根據開啟的example_design配置，合理約束多出來的管腳，比如startup等interface;

  • 根據example的約束進行修改、適配，下面給出SPI配置的示例；

    --# --------------constraints-------------------- #
    set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
    set_property BITSTREAM.CONFIG.CONFIGFALLBACK Enable [current_design]
    --#Expecting type 'enum' with possible values of '3,6,9,12,22,33,40,50,57,69,82,87,90,110,115,130,148'.
    set_property BITSTREAM.CONFIG.CONFIGRATE 90 [current_design]
    set_property CONFIG_VOLTAGE 3.3 [current_design]
    set_property CONFIG_MODE SPIx4 [current_design]
    set_property CFGBVS VCCO [current_design]
    set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
    set_property BITSTREAM.CONFIG.UNUSEDPIN Pulldown [current_design]

    set_property HD.TANDEM_IP_PBLOCK Stage1_Config_IO [get_cells sys_rst_n_IBUF_inst]

    set_property HD.TANDEM_IP_PBLOCK Stage1_Main [get_cells test_i/util_ds_buf]

需要注意的地方有哪些？

  • Tandem技術只在Xilinx較新的器件中支援

  • mcap_design_switch 這個訊號非常有用，可以用作使用者第二階段邏輯的全域性復位訊號；

  • 關於sys_reset復位訊號

    sys_reset 復位訊號最好佈局到BANK65，且使用者自定義IO最好不要放置在BANK65，否則在約束時會引入很多的麻煩；

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