MTK MT8788處理器引數規格介紹

General

-- Tablet, two MCU subsystems architecture

-- Supports eMMC/uFS boot

-- Supports LPDDR3

-- Supports LPDDR4X

AP MCU subsystem

-- Quad-core ARM® 2.0GHz Cortex-A73 MPCoreTM with 64KB L1 I-cache, 64KB L1 D-cache and 1MB unified L2 cache

-- Quad-core ARM® 2.0GHz Cortex-A53 MPCoreTM with 32KB L1 I-cache, 32KB L1 D-cache and 1MB unified L2 cache

-- NEON multimedia processing engine with SIMDv2/VFPv4 ISA support

-- DVFS technology with adaptive operating voltage from 0.6V to 1.12V

MD MCU subsystem

-- Imagination MIPS32® InterAptive processor with max. 864MHz operation frequency

-- High-performance multi-core and multithread processor architecture (two cores and two threads)

-- 32KB L1 I-cache and 32KB L1 D-cache per core

-- 384KB SPRAM (Scratchpad memory, Two-Core’s ISPRAM and DSPRAM)

-- 256KB L2 Cache (share L2 cache for two cores)

-- High-performance AXI bus Interfaces

-- Power management for clock gating control

-- FD216 DSP for running GSM modem with max. 312MHz operation frequency

MD external interfaces

-- Dual SIM/USIM interface

    Interface pins with RF and radio-related peripherals (antenna tuner, PA, etc.)

Security

-- ARM® TrustZone® Security

External memory interface

-- LPDDR3 up to 4GB (single channel with 32-bit data bus width)

-- LPDDR4X up to 8GB (dual channels with 16-bit data bus width)

-- Memory clock up to LPDDR3-1866 or LPDDR4X-3600

-- Self-refresh/partial self-refresh mode

-- Low-power operation

-- Programmable slew rate for memory controller’s IO pads

-- Dual rank memory device

-- Advanced bandwidth arbitration control

Peripherals

-- USB one port with USB3.0 device mode or USB2.0 OTG mode

-- eMMC5.1

-- uFS 2.1

-- 3 UART for debugging and applications

-- 6 SPI masters for external devices

-- 6 I2C/3 I3C to control peripheral devices, e.g. CMOS image sensor, LCM or FM receiver module

-- Max. 3 PWM channels (depending on system configuration/IO usage)

-- I2S for connection with optional external hi-end audio codec

-- GPIOs

-- 2 sets of memory card controllers supporting SD/SDHC/MS/MSPRO/MMC and SDIO2.0/3.0 protocols

Operating conditions

-- Core voltage: 0.7V/0.8V

-- I/O voltage: 1.8V/2.8V/3.3V  

    Memory: 1.1V/0.6V

-- LCM interface: 1.8V

-- Clock source: 26MHz, 32.768kHz

Package

-- Type: VFBGA

-- 11.8mm*11.0mm

-- Height: Max. 0.9mm

-- Ball count: 599 balls

-- Ball pitch: 0.4mm

LTE

-- FDD/TDD Up to 300Mbps downlink, 150Mbps uplink

-- Downlink carrier aggregation (CA) ability; 1.4 to 20MHz RF bandwidth per component carrier (CC) and up to 2 CCs

-- 8*2 downlink SU-MIMO per component carrier

-- Downlink MU-MIMO per component carrier

-- Supports feICIC

-- Supports MBMS

-- Uplink CoMP ability

-- Advanced Interference Cancellation

-- Transmit Atenna Selection

3G UMTS FDD supported features

-- 3G modem supports most main features in 3GPP Release 7 and Release 8

-- CPC (DTX in CELL_DCH, UL DRX DL DRX), HS-SCCH-less, HS-DSCH

-- Dual cell operation

-- MAC-ehs

-- 2 DRX (receiver diversity) schemes in URA_PCH and CELL_PCH

-- Uplink Cat. 7 (16QAM), throughput up to 11.5Mbps

-- Downlink Cat. 24 (64QAM, dual-cell HSDPA), throughput up to 42.2Mbps

-- Fast dormancy

-- ETWS

-- Network selection enhancements

-- Transmit Atenna Selection

TD-SCDMA

-- CDMA/HSDPA/HSUPA baseband

-- TD-SCDMA Bands 34, 39 & 40 and Quad band GSM/EDGE

-- Circuit-switched voice and data; packet switched data 

   384/384Kbps class in UL/DL for TD SCDMA

-- TD-HSDPA: 2.8Mbps DL (Cat.14)

-- TD-HSUPA: 2.2Mbps UL (Cat.6)

-- F8/F9 ciphering/integrity protection

-- Transmit Atenna Selection

Radio interface and baseband front end

-- High dynamic range delta-sigma ADC converts the downlink analog I and Q signals to digital baseband.

-- 10-bit D/A converter for Automatic Power Control (APC)

-- Programmable radio Rx filter with adaptive gain control

-- Dedicated Rx filter for FB acquisition

-- Baseband Parallel Interface (BPI) with programmable driving strength

-- Supports multi-band

GSM modem and voice CODEC

-- Dial tone generation

-- Noise reduction

-- Echo suppression

-- Advanced side-tone oscillation reduction

-- Digital side-tone generator with programmable gain

-- 2 programmable acoustic compensation filters

-- GSM quad vocoders for adaptive multi rate (AMR), enhanced full rate (EFR), full rate (FR) and half rate (HR)

-- GSM channel coding, equalization and A5/1, A5/2 and A5/3 ciphering

-- GPRS GEA1, GEA2 and GEA3 ciphering

-- Programmable GSM/GPRS/EDGE modem

-- Packet switched data with CS1/CS2/CS3/CS4 coding schemes

-- GSM circuit switch data

-- GPRS/EDGE Class 12

CDMA2000 modem interfaces

-- Supports CDMA2000 1xRTT (releases 0) and CDMA2000 HRPD/1xEV-DO Revision 0 and A

-- Supports maximum 1x data rates of 153.6kbps for forward and reverse links and DO data rates of 3.1Mbps for forward link and 1.8Mbps for reverse link

-- Hybrid operation between 1x and HRPD

-- Simultaneous Hybrid Dual Receiver (SHDR) support

-- Supports 1x Diversity

-- Supports SRLTE

-- Transmit Atenna Selection

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注：可參考MT8788規格書（）資料