385FINAL REVIEW之LAB7

385FINAL REVIEW之LAB7

考前晚上寫的（你為啥不早點開始複習啊啊啊），防止自己走神決定邊看記一些東西，寫得可能比較亂大家不要介意！！

歡迎指出錯誤&交流~~

LAB7 IPs and SoCs

7.1 SV 中的testbench （沒空看了）

DELAY TOKEN: #

7.2 實驗概述

• 概括：
  Create a working NIOS II/e based SoC which performs addition from switches into LEDs
  Program must execute from SDRAM (what we will mostly use in this lab,c裡面宣告的變數也是存到SDRAM裡) and use PIO modules wired to LEDs
  QSF檔案： for pin-mapping
  Platform Designer裡面生成的lab7_soc.qsys: the hardware block containing CPU and the supporting hardware (peripherals, memory, etc)，就記一下這個qsys是在platform designer裡生成的吧
  Need to add an I/O constraint for SDRAM

7.3 實驗DEMO要求：

• 一開始是測試讓greenLED閃；

• 之後是重新寫了main.c，按reset會clear accumulator，撥動switch並且按accumulate可以把switch上的值加到accumulator上，accumulator要求是表示0-255unsigned的（加到255以後會overflow），加出來的result是顯示得到了LED小燈上

• 回答他的demo問題

• INPUTS:

1. SYSTEM RESET
2. CLEAR
3. SUM

7.4 概念及重點整理

7.4.1 SoC 系統級晶片:

Motivations: All systems need lots of low performance tasks (getting data in and out of system, formatting data,
debugging, user interface). Therefore, we want to use software for lower performance tasks.

Typical component of an SoC (in lab 7):
CPU, memory, peripherals, accelerators

一些縮寫和備註（有些平時做實驗也沒有管是什麼意思的縮寫今天終於知道他們的全稱了orz）：

• On-Chip memory: RAM, ROM

• PIO module:

as a bridge from AVALON to FPGA logic
PIO modules may be input (to software), output (to FPGA fabric), or bidirectional.

• BSP: Board Support Package
  contains our linker script
  （source file經過compiler變成object file, object file經過linker（linker script）變成hex file）

• PLL: Phase-locked loop 鎖相環，用來統一整合時鐘訊號(generate phase shift–lab7中使得連線到SDRAM的CLOCK相比於SDRAM Controller的clock延遲了3ns，因為controller要經過一個control logic可能會比較複雜有延時)

• IP: Intellectual Property

分為軟IP、固IP和硬IP

IP（智慧財產權）核將一些在數位電路中常用，但比較複雜的功能塊，如FIR濾波器、SDRAM控制器、PCI介面等設計成可修改引數的模組。隨著CPLD/FPGA的規模越來越大，設計越來越複雜（IC的複雜度以每年55%的速率遞增，而設計能力每年僅提高21%），設計者的主要任務是在規定的時間週期內完成複雜的設計。呼叫IP核能避免重複勞動，大大減輕工程師的負擔，因此使用IP核是一個發展趨勢，IP核的重用大大縮短了產品上市時間。

*雖然不是很懂但是看粗體大概明白了是啥意思

IP核有三種不同的存在形式：HDL語言形式，網表形式、版圖形式。分別對應我們常說的三類IP核心：軟核、固核和硬核。 ——FROM 百度百科 IP核

• RTL: Register Transfer Level，暫存器傳輸級 (不關注暫存器和組合邏輯的細節而通過描述暫存器-暫存器之間的邏輯功能描述電路的HDL層次)

#有緣再更系列：
.ELF file
.SDC

7.4.2 SDRAM

1. The full name of SDRAM: Synchronous Dynamic Random Access Memory 同步動態隨機儲存器.

“動態”：Inside the SDRAM, the data is stored in binary by 0 and 1 through capacitors. Since the capacitors keep discharging, we need to charge them frequently, which is the exact meaning of “refreshing”.

“隨機”：自由指定地址讀寫

3. 計算SDRAM的容量：BANK數目 x 行地址 x 列地址 x 資料位寬
   舉例：
   該圖中顯示bank數目= 4，已知行地址13位（2¹³個）列地址10位（2¹⁰），data width為32bit
   則total amount of memory:
   =4x(2¹³)x(2¹⁰)x32bits=1.073e9bits
   =1.073e9/(1024x1024x8)Mbytes=128Mbytes
   =1.073e9/(1024x1024x1024)Gbit=1Gbit

Maximum theoretical transfer rate 計算：
32bits/t_ac(Access time)=32bit/5.5ns=5.18*10^9bits/s

base address: 0x10000000

7.4.3 NIOS II ISA

1. NIOS II/e: IP based 32-bit CPU which can programmed using a high-level language (in this class, we’ll be using C)
2. Use NIOS II as system controller to handle tasks like user interface, data in/outs (do not need high performance) and use accelerator peripheral designed in SV handle high performance operations.
3. <700 LEs: 使用最少的FPGA邏輯和記憶體資源
4. tradeoff: performance vs LEs (resource optimized)

Nios II 經濟型處理器核心的邏輯元件只有 600 個，是微控制器應用的理想選擇。Nios II 經濟型處理器核心、軟體工具和裝置驅動程式均為免費提供。
https://www.intel.cn/content/www/cn/zh/products/programmable/processor/nios-ii.html

5. Configuration:
   
6. USES Modified Harvard RISC architecture

• Von Neumann architecture
  (data和instruction共用memory和bus)
  The same memory and bus are used to store both data and instructions.
  Its drawback is that the CPU is then unable to access program memory and data memory simultaneously.

• Pure Harvard architecture
  (data和instruction用自己各自的memory和bus)
  it stores the instructions and data in different memory
  unit and access them via different buses (physically separated).
  especially powerful in DSP

• Modified Harvard architecture
  the same memory space will store both instructions and data, but they are stored in different blocks (by having separate address spaces and different buses and special instructions).
  一些常值比如pi或者text string可以放在instruction memory裡面，instruction也可以被read as if they were data.

• RISC VS CISC （來不及複習了就標註一下）
  RISC: Reduced Instruction Set Computing
  CISC: Complex Instruction Set Computing

7.4.3 雜雜雜

volatile unsigned int key_reset = (unsigned int)0x70;

被volatile修飾的變數能夠保證每個執行緒能夠獲取該變數的最新值，從而避免出現資料髒讀的現象
https://www.jianshu.com/p/157279e6efdb