The complete timer

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module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output [3:0] count,
    output counting,
    output done,
    input ack );
    reg [9:0] counter;
    reg clkn;
    reg [4:0] delay; // 防 count=4'b1111(4'hf)時，delay=count+4'd1=0溢位。
    reg [3:0] state,next_state;
    parameter [3:0] S = 4'd0,S1 = 4'd1,S11 = 4'd2,S110 = 4'd3,B0 = 4'd4,B1 = 4'd5,B2 = 4'd6,B3 = 4'd7,Count2 = 4'd8,Wait = 4'd9;
    // state transfer
    always@(*) begin
        case(state)
            S: begin
                next_state = (data)? S1:S;
            end
            S1: begin
                next_state = (data)? S11:S;
            end
            S11: begin
                next_state = (data)? S11:S110;
            end
            S110: begin
                next_state = (data)? B0:S;
            end
            B0: begin
                next_state = B1;
            end
            B1: begin
                next_state = B2;
            end
            B2: begin
                next_state = B3;
            end
            B3: begin
                next_state = Count2;
            end
            Count2: begin
                next_state =(delay == 5'd0)? Wait:Count2; 
            end
            Wait: begin
                next_state =(ack)? S:Wait; 
            end
            default: next_state = S;
        endcase
    end
    // flip-flop
    always@(posedge clk) begin
        if(reset)
            state <= S;
        else 
            state <= next_state;
    end
    // output
    always@(posedge clk) begin
        counting <= (next_state == Count2 && !reset)? 1'b1:1'b0; // 這裡記得加條件!reset，否則倒數中途reset需要再多隔1cycle，(先變state再變counting)
        done <= (next_state == Wait)? 1'b1:1'b0;
    end
    
    // shift reg
    always@(posedge clk) begin              
        if(state == B0 || state == B1 || state == B2) begin
            count <= {count[2:0],data};
            delay <= {delay[3:0],data};   
            counter <= 10'd0;
        end  
        else if(state == B3) begin
            count <= {count[2:0],data};
            delay <= {delay[3:0],data} + 4'd1;  
            counter <= 10'd0;
        end
        else if(next_state == Count2) begin           
            count <= (count != 4'd0 && counter == 10'd999)? count - 4'd1:count; // 後者亦滿足當count=0則其一直保持0,只是輸出的形式，真的倒數看delay
            if(delay != 4'd1 && counter == 10'd999) begin //非1的時候，在每一個0進行減
                delay <= delay - 5'd1;
            end
            else if(delay == 5'd1 && counter == 10'd998) begin
                delay <= 5'd0;
            end
            else begin
                delay <= delay;
            end
            counter <= (counter == 10'd999)? 10'd0:counter+10'd1; // frequency divider
        end
        else begin
            counter <= 10'd0;
            count <= 4'd0; // 其他state，count保持0
            delay <= 5'd0;
        end
    end
    
    
endmodule

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