https://www.cnblogs.com/yeungchie/
通過 si 匯出電路網表，實際上在 Virtuoso 中通過選單 File - Export - CDL 和 Calibre LVS 中 Export from schematic viewer 也是通過 si 來匯出電路網表的，下面講下如何使用。
如何執行 si
下面是 si 的執行命令， $cdslibFile 為 cds.lib 檔案。
si -batch -command netlist -cdslib $cdslibFile
si.env 檔案
在 si 的執行路徑下需要提前準備好一個 si.env 檔案，si 通過讀取這個檔案的內容來配置匯出 cdl 所需要的資訊。
檔案的如何編寫可以參考 help 文件：
- Virtuoso Shared Tools
- Design Data Translators Reference
- Design Translation Using CDL Out
- Using CDL Out
- Preparing the si.env File
- Using CDL Out
- Design Translation Using CDL Out
- Design Data Translators Reference
簡單看看就行，我一般是直接通過 GUI 介面嘗試匯出一份 cdl，然後在執行路徑下會有一份 si.env 檔案，下面是一個例子：
simLibName = "stdcel"
simCellName = "TOP"
simViewName = "schematic"
simSimulator = "auCdl"
simNotIncremental = 't
simReNetlistAll = nil
simViewList = '("auCdl" "cdl" "schematic" "cmos_sch" "gate_sch" "cmos.sch" "gate.sch" "symbol")
simStopList = '("auCdl" "cdl")
hnlNetlistFileName = "TOP.cdl"
resistorModel = ""
shortRES = 2000.0
preserveRES = 't
checkRESVAL = 't
checkRESSIZE = 'nil
preserveCAP = 't
checkCAPVAL = 't
checkCAPAREA = 'nil
preserveDIO = 't
checkDIOAREA = 't
checkDIOPERI = 't
checkCAPPERI = 'nil
simPrintInhConnAttributes = 'nil
checkScale = "meter"
checkLDD = 'nil
pinMAP = 'nil
preserveBangInNetlist = 'nil
shrinkFACTOR = 0.0
globalPowerSig = ""
globalGndSig = ""
displayPININFO = 't
preserveALL = 't
setEQUIV = ""
incFILE = "./Subcircuit/3t_device.cdl"
auCdlDefNetlistProc = "ansCdlHnlPrintInst"
這個例子中匯出的頂層電路單元是 stdcel/TOP/schematic，我們只關心其中幾個常用的變數：
- simLibName ( Library Name )
stdcel - simCellName ( Top Cell Name )
TOP - simViewName ( View Name )
schematic - hnlNetlistFileName ( Output CDL Netlist File )
- incFILE ( Include File )
- auCdlDefNetlistProc ( Analog Netlisting Type )
這個變數決定 pin 的連線方式- ansCdlSubcktCall ( Connection By Order )
順序連線 - ansCdlHnlPrintInst ( Connection By Name )
命名埠連線，一般選擇這個來保證 IP/Digital 網表的連線
- ansCdlSubcktCall ( Connection By Order )
Run Directory 直接由 si 的執行路徑來決定。
編寫指令碼 export_cdl
明白了 si 的使用方法，現在可以寫一個 shell 指令碼，在 Terminal 操作，實現便捷地匯出指定電路單元的 cdl 檔案。
點選檢視完整程式碼
#!/bin/bash
#--------------------------
# Program : export_cdl.sh
# Language : Bash
# Author : YEUNGCHIE
# Version : 2022.04.03
#--------------------------
HelpInfo(){
cat <<EOF
-------------------------------------------------
Export CDL ( Circuit Description Language ) File
-------------------------------------------------
Usage: export_cdl -cdslib cdslibFile -lib libName -cell cellName [ OPTIONS ]
-cdslib Path of cds.lib file
-lib Schematic top cell libName
-cell Schematic top cell cellName
-view Schematic top cell viewName ( Default: schematic )
-file Output netlist file name ( Default: ./<cellName>.cdl )
-include Include subckt file name
-order Netlisting Type Connection By Order ( The default is By Name )
-h, --help Display this help
Examples: export_cdl -cdslib ./cds.lib -lib Xeon -cell X999 -include ./subckt.cdl
Output: Netlist file: X999.cdl
EOF
}
viewName='schematic'
connType='ansCdlHnlPrintInst'
# 命令列引數分析
while [[ -n $1 ]]; do
if [[ -n $opt ]]; then
case $opt in
lib_opt) libName=$1 ;;
cell_opt) cellName=$1 ;;
view_opt) viewName=$1 ;;
file_opt) netlistFile=$1 ;;
cdslib_opt) cdslibFile=$1 ;;
include_opt) includeFile=$1 ;;
esac
unset opt
else
case $1 in
-lib) opt='lib_opt' ;;
-cell) opt='cell_opt' ;;
-view) opt='view_opt' ;;
-file) opt='file_opt' ;;
-cdslib) opt='cdslib_opt' ;;
-include) opt='include_opt' ;;
-order)
connType='ansCdlSubcktCall'
;;
-h|--help)
HelpDoc >&2
exit 1
;;
*)
echo "Invalid option - '$1'" >&2
echo "Try -h or --help for more infomation." >&2
exit 1
;;
esac
fi
shift
done
# 引數檢查
if [[ ! ( $cdslibFile && $libName && $cellName ) ]]; then
## 缺少必要引數時，列印 help 並退出
HelpInfo >&2
exit 1
elif [[ -f $cdslibFile ]]; then
## 將相對路徑改為絕對路徑
cdslibDir=$(cd $(dirname $cdslibFile); pwd -P)
fileName=$(basename $cdslibFile)
cdslibFile="$cdslibDir/$fileName"
else
## 找不到 cds.lib 檔案，列印報錯
echo "No such file - $cdslibFile" >&2
echo "Try -h or --help for more infomation." >&2
exit 1
fi
## 當網表檔名未定義時，設定預設檔名
if [[ ! $netlistFile ]]; then netlistFile="${cellName}.cdl" ; fi
# si.env 檔案生成
cat > si.env <<EOF
simLibName = "$libName"
simCellName = "$cellName"
simViewName = "$viewName"
simSimulator = "auCdl"
simNotIncremental = 't
simReNetlistAll = nil
simViewList = '("auCdl" "cdl" "schematic" "cmos_sch" "gate_sch" "cmos.sch" "gate.sch" "symbol")
simStopList = '("auCdl" "cdl")
simNetlistHier = t
hnlNetlistFileName = "$netlistFile"
resistorModel = ""
shortRES = 2000.0
preserveRES = 't
checkRESVAL = 't
checkRESSIZE = 'nil
preserveCAP = 't
checkCAPVAL = 't
checkCAPAREA = 'nil
preserveDIO = 't
checkDIOAREA = 't
checkDIOPERI = 't
checkCAPPERI = 'nil
simPrintInhConnAttributes = 'nil
checkScale = "meter"
checkLDD = 'nil
pinMAP = 'nil
preserveBangInNetlist = 'nil
shrinkFACTOR = 0.0
globalPowerSig = ""
globalGndSig = ""
displayPININFO = 't
preserveALL = 't
setEQUIV = ""
incFILE = ""
auCdlDefNetlistProc = "$connType"
EOF
# 執行 si
si -batch -command netlist -cdslib $cdslibFile
status=$?
# 刪除中間檔案
if [[ -f .stimulusFile.auCdl ]]; then rm -rf .stimulusFile.auCdl ; fi
if [[ -f si.env ]]; then rm -rf si.env ; fi
if [[ -f netlist ]]; then rm -rf netlist ; fi
if [[ -d ihnl ]]; then rm -rf ihnl ; fi
if [[ -d map ]]; then rm -rf map ; fi
exit $status
執行例項
例：cdslib 檔案為 ./cds.lib
-
匯出
verify庫中的ad01d0單元的電路網表。export_cdl -cdslib cds.lib -lib verify -cell ad01d0匯出的 cdl 檔名為
ad01d0.cdl -
匯出
verify庫中的inv0d0單元的電路網表，同時包含 subckt 網表檔案./netlist，並指定 cdl 檔名為inv.cdl。export_cdl -cdslib ./cds.lib -lib verify -cell inv0d0 -include ./netlist匯出的 cdl 檔名為
inv.cdl