See also: PS/2 packet parser.
Now that you have a state machine that will identify three-byte messages in a PS/2 byte stream, add a datapath that will also output the 24-bit (3 byte) message whenever a packet is received (out_bytes[23:16] is the first byte, out_bytes[15:8] is the second byte, etc.).
out_bytes needs to be valid whenever the done signal is asserted. You may output anything at other times (i.e., don't-care).
另請參閱:PS/2 資料包解析器。
現在,您已經擁有了一臺狀態機,該狀態機將識別 PS/2 位元組流中的三位元組訊息,請新增一個資料路徑,該資料路徑也將在收到資料包時輸出 24 位(3 位元組)訊息(out_bytes[23:16] 是第一個位元組,out_bytes[15:8] 是第二個位元組,依此類推)。
每當斷言完成訊號時,out_bytes都需要有效。您可以在其他時間輸出任何內容(即,不在乎)。
題目網站
module top_module(
input clk,
input [7:0] in,
input reset, // Synchronous reset
output [23:0] out_bytes,
output done); //
parameter idle=4'b0001,
first=4'b0010,
second=4'b0100,
third=4'b1000;
reg [3:0]state,nstate;
always@(*)begin
case(state)
idle:begin
if(in[3])begin
nstate=first;
end
else begin
nstate=idle;
end
end
first:nstate=second;
second:nstate=third;
third:begin
if(!in[3])begin
nstate=idle;
end
else begin
nstate=first;
end
end
endcase
end
always@(posedge clk)begin
if(reset)begin
state<=idle;
end
else begin
state<=nstate;
end
end
reg [23:0]data;
assign done=(state==third);
always @(posedge clk) begin
if (reset) begin
data <= 24'd0;
end
else begin
data[23:16] <= data[15:8];
data[15:8] <= data[7:0];
data[7:0] <= in;
end
end
assign out_bytes = (done) ? data : 24'd0;
endmodule
在上一題的基礎上,增加一個資料流錄入的模組