Verilog 監控 Monitor

Monitoring information
Verilog provides a mechanism to monitor a signal when its value changes. This facility is
provided by the $monitor task.
Usage: $monitor(p1,p2,p3,....,pn);
The parameters p1, p2, ... , pn can be variables, signal names, or quoted strings. A format
similar to the $display task is used in the $monitor task. $monitor continuously monitors
the values of the variables or signals specified in the parameter list and displays all
parameters in the list whenever the value of any one variable or signal changes. Unlike
$display, $monitor needs to be invoked only once.

Only one monitoring list can be active at a time. If there is more than one $monitor
statement in your simulation, the last $monitor statement will be the active statement.
The earlier $monitor statements will be overridden.

Two tasks are used to switch monitoring on and off.
Usage:
$monitoron;
$monitoroff;

參考檔案
1：Verilog HDL A Guide to Digital Design and Synthesis, Second Edition  第55頁