verilog學習筆記——三段式狀態機

• https://blog.csdn.net/jason_child/article/details/60466050
  

• 摩爾狀態機的架構 
  

• 狀態轉換圖 
  

• coding

module finite_fsm(
z_o,
clk,
Rst_n,
w_i
);
//輸出埠
output z_o;

//輸入埠
input clk;
input Rst_n;
input w_i;

//輸出埠型別宣告
reg z_o;

//引數宣告
parameter IDLE = 2'b00;
parameter S0 = 2'b01;
parameter S1 = 2'b10;

//內部訊號宣告
reg[1:0] current_state;
reg[1:0] next_state;
//狀態暫存器
always @ (posedge clk or negedge Rst_n) begin
    if(!Rst_n)
            current_state <= IDLE;
    else
        current_state <= next_state;
end
//次態的組合邏輯
always @ (w_i or current_state) begin
    case(current_state)
        IDLE：begin
                  if(w_i) next_state = S0;
                   else   next_state = IDLE;
              end
        S0:  begin
                    if(w_i) next_state = S1;
                    else    next_state = IDLE;
             end
        S1:  begin
                    if(w_i) next_state = S1;
                    else    next_state = IDLE;
             end
        default : next_state = 2'bxx;
   endcase
end
//輸出邏輯
always @ (*) beign
    case(current)
        IDLE:  z_o = 1'b0;
        S0:    z_o = 1'b0;
        S1:    z_o = 1'b1;
        default:  z_0 = 1'b0;
    endcase
end
endmodule

• 關於三段式狀態機的一點總結 
  1確定輸入輸出訊號，及其型別（是wire還是reg）； 
  2宣告內部訊號，一般需要定義current_state和next_state； 
  3用3個always語句描述狀態機;第一個用來次態和現態的轉換，第二個always用於現態在輸入情況下轉換為次態的組合邏輯；第三個語句用於現態到輸出的組合邏輯輸出。