【創龍TMS320C6748開發板試用】+兩張圖，看清時鐘

南方的小清湖發表於2017-01-22
S3
一直在看例程 ，但現例程中沒有時鐘的配置程式，一開始也沒有在意，現在把例程都試差不多了，反回來想想，有點費解。
由於沒有看視訊，今天發現視訊裡有一節是講時鐘的，就下載下來看成了一下。還是挻詳細的。
原來時鐘的配置在gel檔案中。
根據視訊的講解，做了下面兩張圖，算是把時鐘部分的要點總結一下，再深入就是研究DSP的了，而我們這些只是會用就行了。
以下是兩個時鐘PLL0與PLL1的產生。
 

下面是兩個時鐘的一些引數。
 

之於時鐘的配置可以在gel檔案中的device_PLL0與device_PLL1兩個函式中。
  1. device_PLL0(unsigned int CLKMODE, unsigned int PLLM, unsigned int POSTDIV,unsigned int PLLDIV1, unsigned int PLLDIV2, unsigned int PLLDIV3, unsigned int PLLDIV7 ) {

  3.     unsigned int i=0;

  5.     /* Clear PLL lock bit */
  6.     CFGCHIP0 &= ~(0x00000010);

  8.     /* Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled through MMR */
  9.     PLL0_PLLCTL &= ~(0x00000020);

  11.     /* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */
  12.     PLL0_PLLCTL &= ~(0x00000200);

  14.     /* Set PLLEN=0 to put in bypass mode*/
  15.     PLL0_PLLCTL &= ~(0x00000001);

  17.     /*wait for 4 cycles to allow PLLEN mux switches properly to bypass clock*/
  18.     for(i=0; i<PLLEN_MUX_SWITCH; i++) {;}

  20.     /* Select the Clock Mode bit 8 as External Clock or On Chip Oscilator*/
  21.     PLL0_PLLCTL &= 0xFFFFFEFF;
  22.     PLL0_PLLCTL |= (CLKMODE << 8);

  24.     /*Clear PLLRST bit to reset the PLL */
  25.     PLL0_PLLCTL &= ~(0x00000008);

  27.     /* Disable the PLL output*/
  28.     PLL0_PLLCTL |= (0x00000010);

  30.     /* PLL initialization sequence
  31.     Power up the PLL by setting PWRDN bit set to 0 */
  32.     PLL0_PLLCTL &= ~(0x00000002);

  34.     /* Enable the PLL output*/
  35.     PLL0_PLLCTL &= ~(0x00000010);

  37.     /*PLL stabilisation time- take out this step , not required here when PLL in bypassmode*/
  38.     for(i=0; i<PLL_STABILIZATION_TIME; i++) {;}

  40.     /*Program the required multiplier value in PLLM*/
  41.     PLL0_PLLM    = PLLM;

  43.     /*If desired to scale all the SYSCLK frequencies of a given PLLC, program the POSTDIV ratio*/
  44.     PLL0_POSTDIV = 0x8000 | POSTDIV;

  46.     /*Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is currently in progress*/
  47.     while(PLL0_PLLSTAT & 0x1==1){}

  49.     /*Program the RATIO field in PLLDIVx with the desired divide factors. In addition, make sure in this step you leave the PLLDIVx.DxEN bits set so clocks are still enabled (default).*/
  50.     PLL0_PLLDIV1 = 0x8000 | PLLDIV1;             // Fixed Ratio /1
  51.     PLL0_PLLDIV2 = 0x8000 | PLLDIV2;             // Fixed Ratio /2
  52.     PLL0_PLLDIV4 = 0x8000 | (((PLLDIV1+1)*4)-1); // Fixed Ratio /4
  53.     PLL0_PLLDIV6 = 0x8000 | PLLDIV1;             // Fixed Ratio /1
  54.     PLL0_PLLDIV3 = 0x8000 | PLLDIV3;             // Variable Ratio (EMIF)
  55.     PLL0_PLLDIV7 = 0x8000 | PLLDIV7;             // Variable Ratio (RMII)


  58.     /*Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition.*/
  59.     PLL0_PLLCMD |= 0x1;

  61.     /*Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of phase alignment).*/
  62.     while(PLL0_PLLSTAT & 0x1==1) { }

  64.     /*Wait for PLL to reset properly.*/
  65.     for(i=0; i<PLL_RESET_TIME_CNT; i++) {;}

  67.     /*Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset*/
  68.     PLL0_PLLCTL |= 0x8;

  70.     /*Wait for PLL to lock.*/
  71.     for(i=0; i<PLL_LOCK_TIME_CNT; i++) {;}

  73.     /*Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass mode*/
  74.     PLL0_PLLCTL |=  0x1;
  75. }

  77. /**********************************************************************************
  78. DDR PLL1 init:

  80. ***********************************************************************************/
  81. device_PLL1(unsigned int PLLM,unsigned int POSTDIV,unsigned int PLLDIV1, unsigned int PLLDIV2, unsigned int PLLDIV3 ) {

  83.     unsigned int i=0;

  85.     /* Clear PLL lock bit */
  86.     CFGCHIP3 &= ~(0x00000020);

  88.     /* Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled through MMR */
  89.     PLL1_PLLCTL &= ~(0x00000020);

  91.     /* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */
  92.     PLL1_PLLCTL &= ~(0x00000200);

  94.     /* Set PLLEN=0 to put in bypass mode*/
  95.     PLL1_PLLCTL &= ~(0x00000001);

  97.     /*wait for 4 cycles to allow PLLEN mux switches properly to bypass clock*/
  98.     for(i=0; i<PLLEN_MUX_SWITCH; i++) {;}

  100.     /*Clear PLLRST bit to reset the PLL */
  101.     PLL1_PLLCTL &= ~(0x00000008);

  103.     /* Disable the PLL output*/
  104.     PLL1_PLLCTL |= (0x00000010);

  106.     /* PLL initialization sequence
  107.     Power up the PLL by setting PWRDN bit set to 0 */
  108.     PLL1_PLLCTL &= ~(0x00000002);

  110.     /* Enable the PLL output*/
  111.     PLL1_PLLCTL &= ~(0x00000010);

  113.     /*PLL stabilisation time- take out this step , not required here when PLL in bypassmode*/
  114.     for(i=0; i<PLL_STABILIZATION_TIME; i++) {;}

  116.     /*Program the required multiplier value in PLLM*/
  117.     PLL1_PLLM    = PLLM;

  119.     /*If desired to scale all the SYSCLK frequencies of a given PLLC, program the POSTDIV ratio*/
  120.     PLL1_POSTDIV = 0x8000 | POSTDIV;

  122.     /*Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is currently in progress*/
  123.     while(PLL1_PLLSTAT & 0x1==1){}

  125.     /*Program the RATIO field in PLLDIVx with the desired divide factors. In addition, make sure in this step you leave the PLLDIVx.DxEN bits set so clocks are still enabled (default).*/
  126.     PLL1_PLLDIV1 = 0x8000 | PLLDIV1;   // DDR frequency (aka 2X_CLK)
  127.     PLL1_PLLDIV2 = 0x8000 | PLLDIV2;   // Optional CFGCHIP3[ASYNC3_CLKSRC] clock source
  128.     PLL1_PLLDIV3 = 0x8000 | PLLDIV3;   // Optional PLL0 clock source

  130.     /*Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition.*/
  131.     PLL1_PLLCMD |= 0x1;

  133.     /*Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of phase alignment).*/
  134.     while(PLL1_PLLSTAT & 0x1==1) { }

  136.     /*Wait for PLL to reset properly */
  137.     for(i=0; i<PLL_RESET_TIME_CNT; i++) {;}

  139.     /*Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset*/
  140.     PLL1_PLLCTL |= 0x8;

  142.     /*Wait for PLL to lock. See PLL spec for PLL lock time*/
  143.     for(i=0; i<PLL_LOCK_TIME_CNT; i++) {;}

  145.     /*Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass mode*/
  146.     PLL1_PLLCTL |=  0x1;
  147. }
複製程式碼


其實gel檔案中所做的工作還是很多的。之前用28335的時候沒怎麼在意gel檔案，所有的配置都是在C程式中的，看來有必要學習一下gel檔案了。

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